Programmable oscillator circuit and method

• US 6,664,860 B2
• Filed: 01/05/2001
• Issued: 12/16/2003
• Est. Priority Date: 02/05/1997
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Fox Enterprises Incorporated, Jet City Electronics Inc. (Renesas Electronics Corporation)
• Inventors: Trefethan, Eugene S., Fallisgaard, John W.
• Primary Examiner(s): Mis, David C.
• Application Number:
  US09/754,192
• Publication Number:
  US 20010017573A1
• Time in Patent Office: 1,075 Days
• Field of Search: 331/16, 331/18, 331/25, 331/116.R, 331/116.FE, 331/158, 331/179, 327/105, 327/156-159, 375/376, 455/260
• US Class Current: 331/18
• CPC Class Codes: H03B 19/00 Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source transference of modulation from one carrier to another H03D7/00
• CPC Class Codes: H03B 2201/0266 the means comprising a transistor
• CPC Class Codes: H03B 5/366 and comprising means for varying the frequency by a variable voltage or current
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Claims

1. A method of programming an oscillator circuit that outputs a frequency of oscillation, comprising:

providing a phase lock loop for generating an output frequency of oscillation based on an input frequency of oscillation;

adjusting a parameter of the phase lock loop so that the phase lock loop will output a frequency substantially near a predetermined frequency based on the input frequency of oscillation; and

instructing that an impedance be fixed to alter the input frequency of oscillation so that the phase lock loop will substantially output the predetermined frequency.

2. The method of claim 1, wherein the impedance is a capacitance.

3. The method of claim 2, wherein the oscillator circuit is provided in an integrated circuit.

4. A method for an oscillator circuit, comprising:

adjusting the oscillator circuit using an impedance to alter an input frequency of oscillation for the oscillator circuit so as to substantially produce an output of a predetermined frequency; and

operating the oscillator circuit to produce the output, said adjusting and operating steps being distinct in time.

5. A method according to claim 4, wherein the adjusting includes:

providing a phase lock loop for generating a frequency of oscillation based on the input frequency of oscillation; and

instructing that an impedance be fixed to alter the input frequency of oscillation so that the phase lock loop will substantially output the predetermined frequency.

6. A method according to claim 5, wherein the instructing step includes fixing the impedance of a programmable load.

7. A method according to claim 5, wherein the phase lock loop is provided on an integrated circuit.

8. A method according to claim 7, wherein the adjusting step further comprises:

storing values in the integrated circuit to define a multiplication factor of the phase lock loop; and

outputting the values to the phase lock loop.

9. A method according to claim 7, wherein the instructing step includes fixing the impedance of a programmable load, the programmable load being a portion of the integrated circuit.

10. A method according to claim 7, wherein the operating step further comprises:

storing values in the integrated circuit to define a multiplication factor of the phase lock loop; and

outputting the values to the phase lock loop.

11. A method according to claim 4, wherein the impedance is a capacitance.

12. A timing circuit comprising:

a programmable load circuit adapted to be coupled to a crystal to receive a source frequency;

an oscillator circuit adapted to be coupled to receive said source frequency;

a frequency multiplier circuit coupled to said oscillator circuit to receive said source frequency; and

a programming circuit configured to supply stored first programming data to said programmable load circuit to adjust said source frequency and stored second programming data to said frequency multiplier circuit, such that said frequency multiplier circuit supplies an output frequency which is substantially equal to a product of said adjusted source frequency and a multiplication factor designated by said second programming data.

13. A timing circuit in accordance with claim 12, wherein said programmable load circuit is a programmable capacitive load circuit.

14. A timing circuit in accordance with claim 13, wherein said source frequency is adapted to be supplied over a source frequency line adapted to be coupled to said crystal, said programmable capacitive load circuit comprises:

a plurality of capacitors, selected ones of said plurality of capacitors being coupled to said source frequency line.

15. A timing circuit in accordance with claim 14, wherein said programmable capacitive load circuit further comprises:

a plurality of switching elements, each of which having a first terminal connected in common to said source frequency line, and a second terminal coupled to a corresponding one of said plurality of capacitors.

16. A timing circuit in accordance with claim 15, wherein said programming circuit generates a plurality of output signals in accordance with said first programming data stored therein, said plurality of output signals being supplied to said programmable capacitive load circuit to activate selected ones of said plurality of switching elements to connect corresponding ones of said capacitors to said source frequency line.

17. A timing circuit in accordance with claim 15, wherein each of said plurality of switching elements comprises a MOS transistor.

18. A timing circuit in accordance with claim 12, wherein said frequency multiplier circuit includes a phase locked loop circuit.

19. A timing circuit in accordance with claim 12, wherein said second programming data comprises a first parameter P and a second parameter Q, said output frequency (F_out) and said adjusted source frequency (F_adj) satisfying:

20. A timing circuit in accordance with claim 19, wherein said frequency multiplier loop circuit comprises:

a first divider for dividing said adjusted source frequency by a first parameter of said second programming data to generate a first frequency;

a second divider included in said phase locked loop circuit for dividing said output frequency by a second parameter of said second programming data for generating a second frequency; and

a detector included in said phase locked loop circuit and coupled for receiving said first and second frequencies, said detector outputting a control signal in response to said first and second frequencies for controlling a generation of said output frequency.

21. A timing circuit in accordance with claim 20, further comprising:

a third divider circuit, coupled to an output of said phase locked loop circuit and said programming circuit, for dividing said output frequency by a third parameter of said second programming data stored in said programming circuit.

22. A timing circuit in accordance with claim 19, wherein said adjusted source frequency is adapted to be supplied to a divider circuit to generate a loop frequency of said phase locked loop circuit less than 200 KHz.

23. A timing circuit in accordance with claim 22, wherein said loop frequency is within a range of 32 KHz to 50 KHz.

24. A timing circuit in accordance with claim 22, wherein said loop frequency is within a range of 42.395 KHz to 43.059 KHz.

25. A timing circuit in accordance with claim 20, wherein said detector outputs said control signal in accordance with a phase difference between said first and second frequencies, said phase locked loop circuit further comprising:

a charge pump circuit for receiving said control signal and outputting a DC signal in response thereto;

a loop filter; and

a voltage controlled oscillator coupled to said charge pump through said loop filter, said voltage controlled oscillator generating said output frequency under a control of said DC signal.

26. A timing circuit in accordance with claim 12, further comprising a dedicated external programming terminal for entering said first and second programming data for storage in a programmable read only memory included in said programming circuit.

27. A timing circuit in accordance with claim 12, further comprising:

a first PROM for storing signature data;

a program terminal for programming said first PROM with said signature data; and

a first output terminal for reading said signature data out of said first PROM.

28. A timing circuit in accordance with claim 27, further comprising:

a second PROM programmed by said first and second programming data entered through said program terminal; and

a second output terminal for outputting said output frequency and for receiving clock pulses to clock said signature data into said first PROM and to clock said first and second programming data into said second PROM.

29. A timing circuit in accordance with claim 28, further including a second input terminal for receiving clock signals to read said signature data from said first PROM out onto said first output terminal.

37. The programmable crystal oscillator in accordance with claim 26, wherein said input lines are configured to receive an industry standard watch crystal having an associated source frequency of essentially 32.768 KHz.

30. A programmable timing circuit comprising:

an oscillator circuit adapted to be coupled to excite a crystal into generating a source frequency;

a capacitive load circuit adapted to be coupled to said crystal and configured to be programmed by stored programming data to a desired load capacitance, such as to selectively adjust said source frequency; and

a phase locked loop circuit coupled to said oscillator circuit, said phase locked loop circuit for generating an output frequency as a product of said adjusted source frequency and a multiplication factor.

31. A programmable timing circuit in accordance with claim 30, further comprising:

a memory, coupled to said phase locked loop circuit and to said programmable capacitive load circuit, for storing programming data including a first parameter for programming said capacitive load circuit to said desired load capacitance and a second parameter for programming said phase locked loop circuit to said multiplication factor.

32. A programmable timing circuit in accordance with claim 31, wherein said memory comprises a PROM.

33. A programmable timing circuit in accordance with claim 31, wherein said crystal is adapted to be coupled to said oscillator circuit by an input line, said programmable capacitive load circuit comprising:

a plurality of capacitors; and

a plurality of switching elements, each having a first terminal coupled to a corresponding one of said plurality of capacitors and a second terminal coupled to said input line, said memory supplying said first parameter as a plurality of signals to activate selected ones of said plurality of switching elements, thereby coupling said corresponding ones of said plurality of capacitors to said input line.

34. A programmable timing circuit in accordance with claim 33, wherein each of said plurality of switching elements comprises a MOS transistor.

35. A programmable timing circuit in accordance with claim 31, further comprising a dedicated programming terminal accommodating external entry of said programming data for storage in said memory.

36. A programmable oscillator circuit, comprising:

an oscillator circuit;

input lines coupled to said oscillator circuit;

a programmable capacitive load, coupled to said input lines, to provide a load the input lines;

a phase locked loop circuit coupled to the oscillator circuit for generating a loop frequency in response to an output of the oscillator circuit and the programmable capacitive load, said phase locked loop circuit operating on said loop frequency by using a frequency parameter to generate a phase locked loop output frequency; and

a programming circuit coupled to said programmable capacitive load circuit and to said phase locked loop circuit, said programming circuit storing said loading and frequency parameters for respectively programming said capacitive load circuit and said phase locked loop circuit.

38. An electrical-circuit unit for providing an output frequency, comprising:

a programmable load circuit;

an oscillator circuit connected to the programmable load circuit;

a phase lock loop connected to said oscillator circuit for generating a frequency in response to the oscillator circuit and the programmable load circuit;

an electrically-programmable memory for storing first programming data for adjusting said programmable load circuit and for storing second programming data for adjusting said phase lock loop; and

a memory controller for receiving an external input from outside the electrical-circuit unit used in controlling the storage of the first and second programming data.

39. An electrical-circuit unit according to claim 38, wherein the external input includes data specifying the values of the first and second programming data.

40. An electrical-circuit unit according to claim 38, wherein the external input includes a clock signal used in storing the first and second programming data.

41. An electrical-circuit unit according to claim 38, wherein the unit is an electrical-circuit package.

42. An electrical-circuit unit according to claim 41, wherein the package has only four external electrical contacts.

43. An electrical-circuit unit according to claim 41, wherein the package has only six external electrical contacts.

44. An electrical-circuit unit according to claim 38, wherein the unit is an integrated circuit chip.

45. An electrical-circuit unit according to claim 38, wherein the memory stores programming data including a feedback value for the phase lock loop (P), a reference value for the phase lock loop (Q), and oscillator tuning values.

46. An integrated circuit comprising:

a programmable capacitive load circuit including a set of selectable impedances and a set of semiconductor switches, each one of the set of switches coupled respectively to one of the selectable impedances;

an oscillator circuit connected to the programmable load circuit;

a phase lock loop connected to said oscillator circuit for generating a frequency in response to the oscillator circuit and the programmable capacitive load circuit;

a memory for storing first programming data for selecting impedances by turning particular switches of said programmable capacitive load circuit on or off, and for storing a feed back value of the phase lock loop (P) and a reference value for the phase lock loop (Q); and

control logic configured to permit an external input from outside the integrated circuit to cause the memory to store said first programming data, said feedback value (P), and said reference value (Q).

47. A crystal oscillator tuning circuit comprising:

an oscillator circuit adapted to be coupled to a crystal, the oscillator circuit capable of producing a reference frequency;

a programmable capacitor tuning circuit coupled to the oscillator circuit;

a frequency multiplier circuit coupled to the oscillator circuit; and

means for storing data, said means being operatively connected to the programmable capacitor tuning circuit and the frequency multiplier circuit,

wherein the stored data includes data used to selectively adjust the capacitance of the capacitor tuning circuit and data used to selectively adjust the multiplication factor of the frequency multiplier circuit, and

wherein the programmable capacitor tuning circuit and the frequency multiplier circuit are adapted to modify the reference frequency to produce an output clock frequency.

48. A crystal oscillator tuning circuit in accordance with claim 47, wherein said programmable capacitor tuning circuit is a programmable capacitive load circuit.

49. A crystal oscillator tuning circuit in accordance with claim 48, wherein said programmable capacitive load circuit comprises:

a plurality of capacitors adapted to be selectively coupled to an input of said oscillator circuit.

50. A crystal oscillator tuning circuit in accordance with claim 49, wherein said programmable capacitive load circuit further comprises one or more switching elements, each switching element adapted for selectively coupling a respective one of the plurality of capacitors to said input of said oscillator circuit.

51. A crystal oscillator tuning circuit in accordance with claim 50, wherein said data used to selectively adjust the capacitance of the capacitor tuning circuit includes information to select one or more of said plurality of switching elements for connecting corresponding ones of said capacitors to said input of said oscillator circuit.

52. A crystal oscillator tuning circuit in accordance with claim 47, wherein said frequency multiplier circuit includes a phase locked loop circuit.

53. A programmable phase lock loop and oscillator tuning circuit comprising:

an oscillator circuit;

a programmable capacitor load circuit coupled to the oscillator circuit;

a phase lock loop circuit coupled to the oscillator circuit; and

a programmable memory operatively connected to the programmable capacitor load circuit and the phase lock loop circuit,

wherein the memory stores a capacitor load value used to selectively adjust the capacitance of the capacitor load circuit, a feedback value for the phase lock loop (P), and a reference value for the phase lock loop (Q), and

wherein the programmable capacitor load circuit and the phase lock loop circuit are adapted to modify a reference frequency for producing an output frequency.

54. A programmable phase lock loop and oscillator tuning circuit in accordance with claim 53, wherein said programmable capacitor load circuit comprises:

a plurality of capacitors adapted to be selectively coupled to an input of said oscillator circuit.

55. A programmable phase lock loop and oscillator tuning circuit in accordance with claim 54, wherein said programmable capacitor load circuit further comprises one or more switching elements, each switching element adapted for selectively coupling a respective one of the plurality of capacitors to said input of said oscillator circuit.

56. A programmable phase lock loop and oscillator tuning circuit in accordance with claim 55, wherein said capacitor load value includes information to select one or more of said plurality of switching elements for connecting corresponding ones of said capacitors to said input of said oscillator circuit.

57. An electrical-circuit unit for providing an output frequency, comprising:

programmable load circuit means for providing a programmable load;

an oscillator circuit means connected to the programmable load circuit means;

a frequency generating means, including a phase lock loop connected to said oscillator circuit means, for generating a frequency in response to an output of the oscillator circuit means and the programmable load circuit means;

a memory means for storing first programming data for adjusting said programmable load circuit means and for storing second programming data for adjusting said frequency generating means; and

a memory controller means for receiving an external input from outside the electrical-circuit unit to control the storage of the first and second programming data.

58. An electrical-circuit unit according to claim 57, wherein the external input includes data specifying the values of the first and second programming data.

59. An electrical-circuit unit according to claim 57, wherein the external input includes a clock signal used in storing the first and second programming data.

60. An electrical-circuit unit according to claim 57, wherein the unit is an electrical-circuit package.

61. An electrical-circuit unit according to claim 57, wherein the unit is an integrated circuit chip.

62. An electrical-circuit unit according to claim 57, wherein the memory means stores programming data including a feedback value for the phase lock loop (P), a reference value for the phase lock loop (Q), and oscillator tuning values.