Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

• US 6,665,013 B1
• Filed: 05/03/1999
• Issued: 12/16/2003
• Est. Priority Date: 01/28/1994
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Zhou, Zhimin, Nixon, Robert H., Mendis, Sunetra K., Fossum, Eric R., Pain, Bedabrata
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): MISLEH, JUSTIN P
• Application Number:
  US09/305,346
• Time in Patent Office: 1,688 Days
• Field of Search: 257/292, 257/291, 257/294, 250/208.1, 348/294, 348/302, 348/303, 348/304, 348/308, 341/139, 341/142, 341/158, 377/60
• US Class Current: 348/308
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H01L 27/1485 Frame transfer
• CPC Class Codes: H01L 27/14887 Blooming suppression
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Claims

1. An imaging device, comprising:

a semiconductor substrate defining a plurality of pixel cell areas, and a signal handling area;

each said pixel cell area comprising;

a) a photogate overlying said substrate, accumulating photo-generated charge in an underlying portion of said substrate;

b) a charge transfer section, receiving the accumulated photo-generated charge from the photogate; and

c) a coupling section, formed on said substrate adjacent said charge transfer section, having a sensing node connected to said photogate through said charge transfer section, wherein said charge transfer section transfers stored charge from said photogate to said sensing node;

d) a buffer transistor, operating to buffer signal from said sensing node, and a selection transistor, having a gate, operated to select said pixel; and

e) an output node which receives signal only when said selection transistor is operated;

a focal plane array including a plurality of logic units, each unit of said focal plane array including a plurality of said pixel cells, each unit having said output nodes of all of said pixels connected together, and further comprising;

a readout controller, formed in said substrate, which controls readout of said pixel cells to read out one pixel cell from each of the plurality of units, substantially at the same time; and

a plurality of analog to digital converters, formed in said substrate, and each connected to an output node of a unit to read out information from said pixel cells from multiple said units in parallel.

2. An imaging device as in claim 1 further comprising a correlated double-sampling circuit, associated with each of said pixel cells, formed on said substrate.

3. An imaging device, comprising:

a semiconductor substrate defining a plurality of pixel cell areas, and a signal handling area;

each said pixel cell area comprising;

a) a photogate; and

b) a coupling section formed on said substrate adjacent said photogate, having a sensing node connected to receive a signal indicative of photogenerated charge from said photogate and at least one coupling stage, operating to transfer charge from said underlying portion of said substrate to said sensing node;

d) a buffer transistor, operating to buffer signal from said sensing node, and a selection transistor, having a gate, operated to select said pixel; and

e) an output node which receives signal only when said selection transistor is operated.

4. An imaging device comprising a focal plane array of pixel cells, each of said pixel cells including a monolithic semiconductor integrated circuit substrate, each of said pixel cells comprising:

a) a photogate overlying a first portion of said substrate and operating to accumulate photo-generated charge in a first portion of said substrate that underlies said photogate;

b) a charge transfer section, formed in said substrate adjacent said photogate, having a sensing node adjacent said photogate and at least one charge coupling stage, operating to transfer charge from said first portion of said substrate to said sensing node;

c) an output node; and

d) a transistor which selectively connects said sensing node to said output node,

and further comprising a plurality of A/D converters, connected to said output nodes of a plurality of said pixel cells, but less than all of said pixel cells, so that less than all of said pixel cells are attached to said A/D converter.

5. A device as in claim 4 wherein said A/D converter is of a type that averages over a plurality of cycles.

6. A device as in claim 4 wherein said A/D converters are sigma delta A/D converters.

7. A device as in claim 6 wherein each said sigma delta A/D converter includes an analog value summing element with inputs and an output, an integrator, which averages an output of the analog value summing element, a quantizer, which characterizes said output as being either a “

1”

or a “

0”

, an N bit counter which counts a number of times that said quantizer is 1 and a number of times said quantizer is 0, and a D/A converter which produces an analog value based on an output of said quantizer, said analog values being coupled to one of said inputs of said summing element.

8. A device as in claim 7 wherein said quantizer is a single bit quantizer and a D/A converter is a single bit D/A converter.

9. A device as in claim 5 wherein said sigma delta modulator circuit is formed with switched MOS capacitors.

10. A device as in claim 4 wherein said A/D converter uses switched MOS capacitors.

11. A method of forming and using an imaging device, comprising:

defining a plurality of pixel areas, each said pixel area covering a specified area of a charge accumulating substrate;

configuring each of said plurality of pixel areas as a portion of said substrate,

providing a photogate controlling a characteristic of each said portion of said charge accumulating substrate;

providing a sensing node which senses charge in said portion of said charge accumulating substrate;

selectively passing a value in said sensing node to an output node associating an A/D converter circuit with each of a plurality of unit groups of said output nodes of each pixel areas; and

connecting each output node within each said unit group to each other and passing only one output therefrom to said A/D converter to thereby read a plurality of said unit groups in parallel.

12. A method as in claim 11, further comprising subsequently connecting each node of another unit group of sensing nodes to a dedicated A/D converter, to thereby simultaneously read all nodes of said another unit group at once, at a time after said time of reading said each node.