Load testing apparatus, computer readable recording medium for recording load test program, fault diagnosis apparatus, and computer readable recording medium for recording fault diagnosis program

• US 6,665,268 B1
• Filed: 02/25/2000
• Issued: 12/16/2003
• Est. Priority Date: 08/31/1999
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sato, Satoshi, Suzuki, Shintaro
• Primary Examiner(s): Patel, Ajit
• Application Number:
  US09/513,695
• Time in Patent Office: 1,390 Days
• Field of Search: 370/241, 370/242, 370/244, 370/245, 370/252, 714/100, 714/1, 714/25, 714/46, 714/47
• US Class Current: 370/242
• CPC Class Codes: H04L 41/06 Management of faults, events, alarms or notifications
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: Y04S 40/00 Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them

Abstract

In a load testing apparatus, before the load test, three processor elements are combined, without overage or shortage, with a source processor element and a destination processor element as one pair, and the transmission time between the processor elements for each pair is measured. During the load test, packets are sent at a time from the source processor element to the corresponding destination processor element in the same pair, and the transmission time for each pair is measured. The transmission time measured for each pair in the load test is compared with a corresponding expected value data so as to evaluate the performance.

Claims

1. A load testing apparatus which conducts a load test of a parallel processor system, said parallel processor system having

a plurality of arithmetic units each having a packet transmission and receiving function;

and

a network for interconnecting said plurality of arithmetic units;

said load testing apparatus comprising;

a measuring unit which measures the transmission time between a pair of said arithmetic units as an expected value based on the result of combining, without overage or shortage, said plurality of arithmetic units, wherein said pair of said arithmetic units is a combination of an arithmetic unit at the source (source arithmetic unit) and an arithmetic unit at the destination (destination arithmetic unit);

a load test conducting unit which conducts a load test by transmitting a plurality of packets from said plurality of source arithmetic units to the corresponding destination arithmetic units, respectively, based on the result of combining, without overage or shortage, said plurality of arithmetic units into said pairs of arithmetic units, on condition that no packet is transmitted from a plurality of source arithmetic units to a single destination arithmetic unit, and measuring the transmission time between each of said pairs of arithmetic units; and

an evaluation unit which evaluates the performance based on the result of comparing the transmission time for each pair measured by said load test conducting unit with the expected value obtained by said measuring unit for each said pairs of arithmetic units.

2. A load testing apparatus which conducts a load test of a parallel processor system, said parallel processor system having

a plurality of arithmetic units each having a packet transmission and receiving function;

and

a network for interconnecting said plurality of arithmetic units;

said load testing apparatus comprising;

a measuring unit which measures the transmission time between a pair of said arithmetic units as an expected value based on the result of combining, without overage or shortage, said plurality of arithmetic units, wherein said pair of said arithmetic units is a combination of an arithmetic unit at the source (source arithmetic unit) and an arithmetic unit at the destination (destination arithmetic unit);

a load test conducting unit which conducts a load test by transmitting a plurality of packets from said plurality of source arithmetic units to the corresponding destination arithmetic units, respectively, in such a timing as to arrive at said network at the same time point based on the result of combining, without overage or shortage, said plurality of arithmetic units into said pairs of arithmetic units, on condition that no packet is transmitted from a plurality of source arithmetic units to a single destination arithmetic unit, and measuring the transmission time between each of said pairs of arithmetic units; and

an evaluation unit which evaluates the performance based on the result of comparing the transmission time for each pair measured by said load test conducting unit with the expected value obtained by said measuring unit for each said pairs of arithmetic units.

3. A load testing apparatus which conducts a load test of a parallel processor system, said parallel processor system having

a plurality of arithmetic units each having a packet transmission and receiving function;

and

a network for interconnecting said plurality of arithmetic units;

said load testing apparatus comprising;

a measuring unit which measures the transmission time between a pair of said arithmetic units as an expected value based on the result of combining, without overage or shortage, said plurality of arithmetic units, wherein said pair of said arithmetic units is a combination of an arithmetic unit at the source (source arithmetic unit) and an arithmetic unit at the destination (destination arithmetic unit);

a load test conducting unit which conducts a load test by transmitting a packet from the source arithmetic unit of a specific pair for which the transmission time is longer than for the other pairs to the corresponding destination arithmetic unit while transmitting packets, at a time, from said plurality of source arithmetic units of the other pairs to the corresponding destination arithmetic unit based on the result of combining, without overage or shortage, said plurality of arithmetic units into said pairs of arithmetic units, on condition that no packet is transmitted from a plurality of source arithmetic units to a single destination arithmetic unit, and measuring the transmission time between each of said pairs of arithmetic units and the transmission time between said specific set of arithmetic unit; and

an evaluation unit which evaluates the performance based on the result of comparing the transmission time for each of the other pairs and said specific pairs measured by the load test conducting unit with the expected values corresponding to said each of the other pairs and said specific pairs, respectively.

4. A computer readable recording medium for recording a load test program used for a load test of a parallel processor system including a plurality of arithmetic units each having a packet transmission and receiving function and a network for interconnecting said plurality of arithmetic units, said load test program enabling the computer to execute the steps of:

measuring the transmission time between a pair of said arithmetic units as an expected value based on the result of combining, without overage or shortage, said plurality of arithmetic units, wherein said pair of said arithmetic units is a combination of an arithmetic unit at the source (source arithmetic unit) and an arithmetic unit at the destination (destination arithmetic unit);

conducting a load test by transmitting a plurality of packets at a time from said plurality of source arithmetic units to the corresponding destination arithmetic units, respectively, based on the result of combining, without overage or shortage, said plurality of arithmetic units into said pairs of arithmetic units, on condition that no packet is transmitted from a plurality of source arithmetic units to a single destination arithmetic unit, and measuring the transmission time between each of said pairs of arithmetic units; and

evaluating the performance based on the result of comparing the transmission time for each pair measured in said load test conducting step with the expected value obtained by said measuring unit for each said pairs of arithmetic units.

5. A computer readable recording medium for recording a load test program used for a load test of a parallel processor system including a plurality of arithmetic units each having a packet transmission and receiving function and a network for interconnecting said plurality of arithmetic units, said load test program enabling the computer to execute the steps of:

a measuring unit which measures the transmission time between a pair of said arithmetic units as an expected value based on the result of combining, without overage or shortage, said plurality of arithmetic units, wherein said pair of said arithmetic units is a combination of an arithmetic unit at the source (source arithmetic unit) and an arithmetic unit at the destination (destination arithmetic unit);

conducting a load test by transmitting a plurality of packets at a time from said plurality of source arithmetic units to the corresponding destination arithmetic units, respectively, in such a timing as to arrive at said network at the same time point, based on the result of combining, without overage or shortage, said plurality of arithmetic units into said pairs of arithmetic units, on condition that no packet is transmitted from a plurality of source arithmetic units to a single destination arithmetic unit, and measuring the transmission time between each of said pairs of arithmetic units; and

evaluating the performance based on the result of comparing the transmission time for each pair measured in said load test conducting step with the expected value obtained by said measuring unit for each said pairs of arithmetic units.

6. A computer readable recording medium for recording a load test program used for a load test of a parallel processor system including a plurality of arithmetic units each having a packet transmission and receiving function and a network for interconnecting said plurality of arithmetic units, said load test program enabling the computer to execute the steps of:

measuring the transmission time between a pair of said arithmetic units as an expected value based on the result of combining, without overage or shortage, said plurality of arithmetic units, wherein said pair of said arithmetic units is a combination of an arithmetic unit at the source (source arithmetic unit) and an arithmetic unit at the destination (destination arithmetic unit);

conducting a load test by transmitting a packet from the source arithmetic units of a specific pair for which the transmission time is longer than for the other pairs to the corresponding destination arithmetic unit while transmitting packets, at a time, from said plurality of source arithmetic units of the other pairs to the corresponding destination arithmetic unit based on the result of combining, without overage or shortage, said plurality of arithmetic units into said pairs of arithmetic units, on condition that no packet is transmitted from a plurality of source arithmetic units to a single destination arithmetic unit, and measuring the transmission time between each of said pairs of arithmetic units and the transmission time between said specific set of arithmetic unit; and

evaluating the performance based on the result of comparing the transmission time for said specific pairs and the transmission time for each of the other pairs measured in the load test conducting step with said expected values corresponding to said specific pairs and each of the other pairs, respectively.