Full duplex transceiver

• US 6,665,276 B1
• Filed: 02/24/2000
• Issued: 12/16/2003
• Est. Priority Date: 02/24/2000
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Culbertson, David L., Travelyn, Raymond F.
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Levitan, Dmitry
• Application Number:
  US09/513,740
• Time in Patent Office: 1,391 Days
• Field of Search: 370/276, 370/278, 370/282, 455/73, 455/82, 455/83, 455/85, 455/557
• US Class Current: 370/282
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A RF front end to an IF generator and post-processor whereby the IF generator output is variable. The transceiver up-conversion path includes an IF Filter, the output of which is input to a mixer with the output of a fixed Phase Locked Oscillator (PLO). The mixer output is input to a band-pass filter and amplified. With a single antenna configuration, the amplifier output connects to either an internal or external diplexer that interfaces to the antenna. With a dual antenna configuration, the amplifier output interfaces directly to the antenna. Similarly, the down-conversion path includes an internal or external diplexer in the single antenna configuration, a band-pass filter, a RF amplifier, a mixer that receives the RF amplifier output and the fixed PLO as inputs, an IF Filter, IF amplifier, and an attenuator for interfacing to the IF post-processor. A user-interface allows RF TX and RX frequency selection, data rate selection, and configurable options including internal or external diplexer, internal or external oscillator reference, and TX amplifier keying to allow simplex, half duplex, or full duplex communication.

Claims

1. The transceiver system capable of simplex, half-duplex, or full duplex operation, comprising:

a variable Intermediate Frequency (IF) generator and post-processor;

a user-interface;

a transceiver, said transceiver further comprising;

an embedded controller;

a first interface between said embedded controller and said variable IF generator and post-processor;

a distinct second interface between said variable IF generator and post-processor and said transceiver, said distinct second interface to transfer variable transmit (TX) IF signals from said variable IF generator and post-processor to said transceiver, and said distinct second interface to transfer said receive (RX) IF signals from said transceiver to said variable IF generator and post processor;

a distinct third interface between said embedded controller and said external user-interface;

at least one antenna interface;

an up-conversion path to convert said variable TX IF signals to TX Radio Frequency (RF) signals, said up-conversion path further comprising at least one fixed Phase Locked Oscillator (PLO), a transmit (TX) IF filter, said TX IF filter input being said variable TX IF signals generated by said variable IF generator and post-processor, a TX mixer having a first input and a distinctive second input, said first input being said TX IF filter output, said second input being one of said at least one fixed PLO output, a TX band-pass filter (BPF) connected to said TX mixer output, a TX amplifier connected to said TX BPF output, said TX amplifier configurable for constant on, constant off, or request to send (RTS) control, said up-conversion path connecting said TX RF signals to one of said at least one antenna interface;

a down-conversion path connected to one of said at least one antenna interface, said down-conversion path to convert received (RX) RF signals to said RX IF signals, said down-conversion path further comprising said at least one fixed PLO, a receive (RX) BPF, said RX BPF input being said RX RF signals, a RX amplifier connected to said RX BPF output, a RX mixer having a first input and a distinctive second input, said first input being said RX amplifier output, said second input being one of said at least one fixed PLO output, a RX IF Filter connected to said RX mixer output, and a RX IF amplifier connected to said RX IF Filter output;

a distinct fourth interface between said embedded controller and said transmit (TX) band-pass filter (BPF);

a distinct fifth interface between said embedded controller and said receive (RX) BPF;

a distinct sixth interface between said embedded controller and said TX amplifier;

a distinct seventh interface between said embedded controller and an internal diplexer, said internal diplexer further comprising an internal diplexer TX terminal, an internal diplexer RX terminal, and an internal diplexer common terminal;

an external diplexer interface, said external diplexer interface further comprising an external diplexer interface TX terminal, an external diplexer interface RX terminal, and an external diplexer common terminal;

an internal oscillator reference to drive said at least one PLO;

an external oscillator reference interface to allow said at least one PLO to be driven by an external oscillator; and

,

a distinct eighth interface between said embedded controller and said internal oscillator.

2. The transceiver system of claims 1, wherein said down-conversion path further comprises an attenuator connected to said RX IF amplifier output.

3. The transceiver system of claim 2, wherein said attenuator is a digital attenuator, and wherein said transceiver further comprises a distinct eighth interface between said digital attenuator and said embedded controller.

4. The transceiver system of claim 3, wherein said distinct second interface further comprises:

a TX IF interface between said TX IF filter and said variable IF generator and post-processor; and

,

a RX IF interface between said attenuator and said variable IF generator and post-processor.

5. The transceiver system of claim 4, wherein said at least one antenna interface further comprises:

a single antenna interface; and

a dual antenna interface.

6. The transceiver system of claim 5, wherein:

said single antenna interface is configurable; and

,

said dual antenna interface further comprises a TX terminal and a RX terminal.

7. The transceiver system of claim 6, further comprising:

a first relay, said first relay input connected to said TX amplifier output;

a distinct second relay, said second relay output connected to said RX BPF input;

a distinct third relay, said third relay output connected to said single antenna interface; and

a distinct fourth relay, said fourth relay having a first input and a distinct second input, said first input connected to said internal oscillator reference, said second input connected to said external oscillator reference interface, said fourth relay output connected to said one of at least one fixed PLO.

8. The transceiver system of claim 7, wherein:

said single antenna interface further comprises a first configuration and a distinct second configuration, said first configuration further comprising said first relay output connected to said internal diplexer TX terminal, said internal diplexer combined terminal connected to said third relay input, and said internal diplexer RX terminal connected to said second relay input, said distinct second configuration further comprising said first relay output connected to said external diplexer interface TX terminal, said external diplexer interface combined terminal connected to said third relay input, and said external diplexer RX terminal connected to said second relay input; and

said dual antenna interface further comprises said first relay output connected to said dual antenna interface TX terminal, and said second relay input connected to said dual antenna RX terminal.

9. The transceiver system of claim 8, wherein said variable IF generator and post-processor further comprises a modem.