Digital matched filter circuit employing analog summation

• US 6,665,358 B1
• Filed: 02/16/2000
• Issued: 12/16/2003
• Est. Priority Date: 03/29/1999
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Odagiri, Hideaki
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): ODOM, CURTIS B
• Application Number:
  US09/504,495
• Time in Patent Office: 1,399 Days
• Field of Search: 375/343, 375/364, 375/149, 375/142, 375/152, 370/342, 348/697, 342/450
• US Class Current: 375/343
• CPC Class Codes: H04B 1/7093 Matched filter type

Abstract

A digital matched filter stores a series of values of a digital input signal in a memory, compares each stored value with a corresponding value of a known code, and generates an analog comparison result signal for each comparison. The analog comparison result signals are combined to obtain an analog sum signal, which is then converted to a digital output signal. The digital output signal is obtained in real time, because there is little or no processing delay in combining the analog comparison result signals. The circuits that generate and combine the analog comparison result signals are similar to digital circuits, enabling the digital matched filter to be integrated easily with other digital signal-processing circuits.

Claims

1. A method of correlating a digital input signal with a known code, comprising the steps of:

(a) storing a series of values of the digital input signal in a memory;

(b) comparing each stored value of the digital input signal with a corresponding value of the known code;

(c) generating respective analog comparison result signals for all said stored values simultaneously and switching a plurality of current sources on and off according to comparison results obtained in said step (b);

(d) combining the analog comparison result signals to obtain an analog sum signal, wherein the analog comparison result signals are current signals; and

(e) converting the analog sum signal to a digital output signal.

2. The method of claim 1, wherein said step (d) further comprises the step of supplying currents from the current sources in parallel to a current mirror circuit.

3. A method of correlating a digital input signal with a known code, comprising the steps of:

(a) storing a series of values of the digital input signal in a memory

(b) comparing each stored value of the digital input signal with a corresponding value of the known code;

(c) generating respective analog comparison result signals for all said stored values simultaneously;

(d) combining the analog comparison result signals to obtain an analog sum signal, wherein the analog comparison result signals are voltage signals represented by charges stored in a plurality of capacitors; and

(e) converting the analog sum signal to a digital output signal.

4. The method of claim 3, wherein said step (c) further comprises the steps of:

dividing the plurality of capacitors into a first group and a second group according to comparison results obtained in said step (b);

charging the capacitors in the first group to a first potential; and

discharging the capacitors in the second group to a second potential.

5. The method of claim 4, wherein said step (d) further comprises the step of interconnecting the plurality of capacitors, thereby obtaining, as the analog sum signal, a voltage signal proportional to a total charge stored in the plurality of capacitors.

6. A method of correlating a digital input signal with a known code, comprising the steps of:

(a) storing a series of values of the digital input signal in a memory;

(b) comparing each stored value of the digital input signal with a corresponding value of the known code;

(c) generating respective analog comparison result signals for all said stored values simultaneously;

(d) combining the analog comparison result signals to obtain an analog sum signal, wherein each analog comparison result signal among the analog comparison result signals is a multi-level signal representing a difference between one the stored value of the digital input signal and the corresponding value of the known code; and

(e) converting the analog sum signal to a digital output signal.

7. The method of claim 6, wherein each said stored value has assign bit, and for each said stored value, said step (c) further comprises the steps of:

generating a first analog signal proportional to a sum of an absolute amplitude of said stored value and a maximum possible amplitude of the digital input signal;

generating a second analog signal proportional to a difference between said absolute amplitude and said maximum possible amplitude; and

selecting one of the first analog signal and the second analog signal, depending on agreement of the sign bit of said stored value with the corresponding value of the known code.

8. A digital matched filter for comparing a digital input signal with a known code, comprising:

a code generator generating the known code;

a plurality of unit processing circuits coupled to the code generator, storing respective values of the digital input signal, comparing the stored values with corresponding values of the known code, and generating respective current signals indicating comparison results;

a current summing circuit coupled to the plurality of unit processing circuits, summing said current signals to obtain an output current signal; and

an analog-to-digital converter coupled to the current summing circuit, converting the output current signal to a digital output signal;

wherein each one of the unit processing circuits separately comprises;

a memory circuit storing one bit of the digital input signal;

a logic gate performing an exclusive logical operation on said one bit of the digital input signal and a corresponding bit of the known code; and

a digital-to-analog converter converting an output of the logic gate to one of said current signals.

9. The digital matched filter of claim 8, wherein the digital-to-analog converter comprises:

a current source; and

a transistor coupled to the current source, switched on and off by the output of said logic gate.

10. A digital matched filter for comparing a digital input signal with a known code, comprising:

a code generator generating the known code;

a plurality of unit processing circuits coupled to the code generator, storing respective values of the digital input signal, comparing the stored values with corresponding values of the known code, and generating respective current signals indicating comparison results;

a current summing circuit coupled to the plurality of unit processing circuits, summing said current signals to obtain an output current signal; and

an analog-to-digital converter coupled to the current summing circuit, converting the output current signal to a digital output signal;

wherein each one of the unit processing circuits separately comprises;

a memory circuit storing one value of the digital input signal; and

a digital-to-analog converter generating, as one of said current signals, a current representing a difference between the value stored in the memory circuit and a corresponding value of the known code.

11. The digital matched filter of claim 10, wherein:

said one value of the digital input signal has a sign bit representing a sign of the digital input signal, and at least one amplitude bit representing an amplitude of the digital input signal;

said one of the unit processing circuits also has a logic gate performing an exclusive logical operation on said sign bit and the corresponding value of the known code; and

the digital-to-analog converter generates a first current representing a difference between the amplitude of the digital input signal and a maximum possible amplitude of the digital input signal, and a second current representing a sum of the amplitude of the digital input signal and said maximum possible amplitude, and has a switch, controlled by an output of said logic gate, for selecting one of the first current and the second current.

12. A digital matched filter for comparing a digital input signal with a known code, comprising:

a code generator generating the known code;

a memory circuit storing a plurality of values of the digital input signal;

a plurality of capacitors;

a plurality of logic circuits coupled to the code generator, the memory circuit, and respective capacitors, comparing respective values of the digital input signal with corresponding values of the known code, thereby obtaining comparison results, and charging and discharging the capacitors according to the comparison results;

an interconnecting circuit switchably interconnecting the capacitors, thereby obtaining an analog voltage signal representing a total charge stored in the capacitors; and

an analog-to-digital converter coupled to the interconnecting circuit, converting the analog voltage signal to a digital output signal.

13. The digital matched filter of claim 12, wherein each one of said logic circuits separately comprises:

a first transistor for discharging one of the capacitors;

a logic gate performing an exclusive logical operation on one bit of the digital input signal and a corresponding bit of the known code; and

a second transistor for charging one of the capacitors, responsive to an output of the logic gate.

14. The digital matched filter of claims 12, wherein each one of said logic circuits is coupled to more than one of the capacitors and stores, in the coupled ones of the capacitors, a total charge representing a difference between one value of the digital input signal stored in the memory circuit and one corresponding value of the known code.

15. The digital matched filter of claim 14, wherein:

said one value of the digital input signal has a sign bit representing a sign of the digital input signal, and at least one amplitude bit representing an amplitude of the digital input signal, and each one of said logic circuits comprises;

a first logic gate performing an exclusive logical operation on the sign bit and the corresponding value of the known code, storing a charge representing a maximum possible amplitude of the digital input signal in a first group of the capacitors, conditional on agreement of the sign bit with the corresponding value of the known code; and

at least one second logic gate performing an exclusive logic operation on said amplitude bit and an output of the first logic gate, storing in a second group of the capacitors a charge representing the amplitude of the digital input signal if the output of the first logic gate has one value, and a complement of the amplitude of the digital input signal if the output of the first logic gate has another value.

16. The digital matched filter of claim 12, wherein the digital input signal is a code division multiple access signal.

17. The digital matched filter of claim 12, wherein the known code is a pseudorandom noise code.