System and method for waveform processing

• US 6,665,621 B2
• Filed: 07/27/2001
• Issued: 12/16/2003
• Est. Priority Date: 11/28/2000
• Status: Expired due to Term

• Current Assignee: Omron Scientific Technologies Incorporated (Omron Corporation)
• Original Assignee: Scientific Technologies Incorporated (Omron Corporation)
• Inventors: Cardona, Javier Onses, Drinkard, John J., Dums, Christopher Alan
• Primary Examiner(s): SHAH, KAMINI S
• Application Number:
  US09/917,477
• Publication Number:
  US 20020065620A1
• Time in Patent Office: 872 Days
• Field of Search: 702/66, 702/176, 702/177, 375/359, 375/360, 375/361, 327/165, 327/198, 327/291, 327/261, 327/262, 327/285
• US Class Current: 702/66
• CPC Class Codes: G01R 13/345 for displaying sampled signals by using digital processors by intermediate A.D. and D.A. convertors (control circuits for CRT indicators)
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test

Abstract

A data reduction circuit serves as a post-processor for digitized waveform data, providing reduced data sets for subsequent processing. Preferably, the data reduction circuit receives one or more potentially long sequences of digital waveform data and provides as output sets of sequence numbers corresponding to transitions in the digitized waveforms. In this manner, a processor concerned with the location of waveform transitions is relieved from the burden of processing the sequences just to identify the transition points. In some embodiments, the data reduction circuit cooperates with a waveform digitizer that produces digitized sequences of comparator waveforms in a laser-based distance measuring circuit. Transition points in the digitized waveform correspond to return reflections of emitted laser pulses and may be used to identify laser pulse flight time. Thus, reporting only sequence numbers for the waveform transition points greatly reduces the amount of data transferred to a distance-calculating processor.

Claims

1. A circuit receiving a sequence of binary digits representing a waveform and generating a reduced output for further processing, said reduced output comprising a set of sequence numbers corresponding to transitions in said sequence of binary digits, said circuit comprising:

a first data interface operative to receive said sequence of binary digits;

a second data interface operative to output said set of sequence numbers; and

processing logic operative to generate said set of sequence numbers by processing said sequences of binary digits.

2. The circuit of claim 1 wherein said circuit comprises a field programmable gate array (FPGA).

3. The circuit of claim 1 wherein said circuit comprises a complex programmable logic device (CPLD).

4. The circuit of claim 1 wherein said circuit comprises an application specific integrated circuit (ASIC).

5. The circuit of claim 1 further comprising a waveform digitizer operative to generate said sequence of binary digits based on digitizing an input waveform.

6. The circuit of claim 5 wherein said waveform digitizer comprises a digital delay line-based waveform capture circuit operative to sample the input waveform at discrete sample times corresponding to successive delay taps defined by said digital delay line.

7. The circuit of claim 1 wherein said first data interface comprises:

an address generator and associated address bus operative to generate address values for reading out said sequence of binary digits from memory address locations in an associated waveform digitizer storing said sequence of binary digits; and

a data bus operative to receive said sequence of binary digits read out from the waveform digitizer.

8. The circuit of claim 1 wherein said second data interface comprises a read interface operative to interface said circuit with an associated processor, such that the associated processor can read out said set of sequence numbers from said circuit.

9. The circuit of claim 8 wherein said second data interface comprises data memory operative to hold said set of sequence numbers for transfer to the associated processor.

10. The circuit of claim 1 wherein said processing logic comprises an arrangement of logic circuits operative to identify transition points in said sequence of binary digits.

11. The circuit of claim 10 wherein said logic circuits comprise logic gates operative to generate cluster data identifying sequence numbers corresponding to said transition points.

12. The circuit of claim 10 wherein said logical circuits comprise logic gates operative to generate sets of sequence numbers as sequence number pairs based on identifying a first transition in said sequence of binary digits where said binary digits change from a first value to a second value, and identifying a second, subsequent transition where said binary digits change back to said first value.

13. The circuit of claim 12 wherein said first data interface further comprises data memory, and wherein said logic gates further comprise memory interface circuits operative to write said sequence number pairs into said data memory.

14. A circuit comprising:

a digital delay-line based waveform digitizer operative to generate a sequence of binary digits based on sampling an input waveform at discrete sample points timed by said digital delay line; and

a data reduction circuit operative to receive said sequence of binary digits from said waveform digitizer and to generate sets of sequence numbers corresponding to transitions within said sequence of binary digits.

15. The circuit of claim 14 wherein said data reduction circuit comprises a logic device operative to identify sequence numbers corresponding to said transitions within said sequence of binary digits, wherein a sequence number identifies a position of a binary digit within said sequence of binary digits representing a transition from a first binary value to a second binary value.

16. The circuit of claim 14 wherein said data reduction circuit comprises a field programmable gate array (FPGA).

17. The circuit of claim 14 wherein said data reduction circuit comprises a complex programmable logic device (CPLD).

18. The circuit of claim 14 wherein said data reduction circuit comprises an application specific integrated circuit (ASIC).

19. The circuit of claim 14 wherein said waveform digitizer and said data reduction circuit comprise portions of an integrated circuit device.

20. The circuit of claim 14 wherein said data reduction circuit comprises processing logic operative to identify pairs of sequence numbers corresponding to a first transition in said sequence of binary digits from a first digital value to a second digital value, and to a second, subsequent transition back to said first digital value.

21. The circuit of claim 20 wherein said data reduction circuit further comprises data memory operative to hold said pairs of sequence numbers.

22. The circuit of claim 21 wherein said data reduction circuit further comprises a first data interface operative to interface said data memory to an external processor.

23. The circuit of claim 14 wherein said waveform digitizer comprises:

a digital delay line comprising a succession of inter-connected delay stages, each said delay stage providing a delay tap output signal corresponding to a delay line sample time; and

at least one capture channel comprising a set of digital capture registers, each said digital capture register having a data input commonly connected to a waveform input, and having a capture clock input individually connected to a respective one of said delay tap output signals, such that each said capture register records a binary state of an input waveform at one of said delay line sample times;

wherein said capture channel captures said sequence of binary digits processed by said data reduction circuit.

24. The circuit of claim 14 wherein said data reduction circuit comprises:

a first data interface operative to store said set of sequence numbers, and to transfer said set of sequence numbers to an external processor;

a second data interface operative to receive said sequence of binary digits from said waveform digitizer; and

processing logic operative to generate said set of sequence numbers based on processing said sequence of binary digits.

25. A method of reducing data transfer between a waveform digitizer that digitizes a waveform as a sequence of binary values and an associated processor concerned with processing the binary values, the method comprising:

determining which binary values in said sequence of binary values represent waveform transition points;

storing sequence numbers for said binary values corresponding to said transition points; and

transferring said sequence numbers to the associated processor.

26. The method of claim 25 further comprising generating said sequence of binary values based on sampling an input waveform at discrete sampling points.

27. The method of claim 26 wherein sampling an input waveform at discrete sampling points comprises recording digital samples of said input waveform at sampling intervals determined by a digital delay line, wherein said digital delay line comprises successive delay stages, each successive delay stage representing a successive delay interval.

28. The method of claim 25 further comprising determining pairs of sequence numbers corresponding to a related pair of transitions in said sequence of binary values.

29. The method of claim 28 further comprising transferring said pairs of sequence numbers to the associated processor.

30. The method of claim 25 further comprising determining sequence numbers corresponding to one or more transition points in a plurality of sequences of binary values corresponding to a like plurality of digitized waveforms.

31. The method of claim 25 further comprising identifying a pulse width of a pulse in said digitized waveform by identifying a first digital value in said sequence of digital values corresponding to a change in said digital values from a first value to a second value, and identifying a second, subsequent digital value corresponding to change in said digital value back to said first value.

32. The method of claim 31 further comprising storing a pair of sequence numbers corresponding to said first and second digital values.

33. The method of claim 32 further comprising storing a plurality of pairs of sequence numbers corresponding to pluralities of associated said first and second digital values.