Interrupt driven interface coupling a programmable media access controller and a process controller

• US 6,665,752 B1
• Filed: 03/01/2000
• Issued: 12/16/2003
• Est. Priority Date: 02/17/2000
• Status: Expired due to Term

• Current Assignee: MaxLinear Communications, LLC (f/k/a Entropic Communications, LLC) (Maxlinear Incorporated)
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Bansal, Sahil, Goldenberg, Moshe, Bernath, Brett A.
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): KIM, HAROLD J
• Application Number:
  US09/516,465
• Time in Patent Office: 1,385 Days
• Field of Search: 710/8, 710/10, 710/11, 710/56, 710/52, 710/200, 710/260, 709/200
• US Class Current: 710/52
• CPC Class Codes: H04L 12/2801 Broadband local area networks

Abstract

An interrupt driven interface coupling a programmable media access controller (MAC) and a process controller. The interrupt driven interface is operable within a cable modem system. The specification by which the cable modem operates to transfer data between the programmable media access controller (MAC) and the control processor is loaded into a memory location within the system, and the physical system is operable to provide for backward compatibility, in that, the addition of new messages and the deletion of old messages within the specification is performed via software upgrade. The necessity of a re-design and re-fabrication of the programmable media access controller (MAC) and the control processor, and the interface between them is completely obviated by the present invention.

Claims

1. A cable modem system that interfaces at least two processors to transfer data between the at least two processors, the cable modem system comprising:

a first processor;

a second processor;

a memory that stores a specification within a first portion of the memory, the specification governs the transfer of the data between the first processor and the second processor, one of the first processor and the second processor writes the data to a second portion of the memory;

a semaphore circuitry determines which of the first processor and the second processor writes the data to the second portion of the memory;

an interrupt control circuitry that notifies the other of the first processor and the second processor to read the data from the second portion of the memory; and

a bus that communicatively couples the first processor, the second processor, the semaphore circuitry, the interrupt control circuitry, and the memory.

2. The cable modem system of claim 1, wherein the memory is, at least in part, a flash memory;

and

the specification is stored within the flash memory.

3. The cable modem system of claim 1, wherein the memory is, at least in part, a random access memory, the random access memory is partitioned into a plurality of buffers, each of the plurality of buffers having a size and a location.

4. The interrupt driven interface of claim 3, wherein the size and the location of each of the plurality of buffers is adjustable to conform with the specification.

5. The cable modem system of claim 1, wherein the specification is loaded into the memory using an external and portable media.

6. The cable modem system of claim 1, wherein the first processor and the second processor are embedded within a single circuitry.

7. The cable modem system of claim 1, wherein the first processor is contained within a cable modem;

the second processor is contained within a peripheral device; and

the bus communicatively couples the cable modem and the peripheral device.

8. The cable modem system of claim 1, wherein each of the first processor and the second processor is operable to perform a plurality of processes, each process being defined by the specification.

9. A cable modem system for providing an external system access to a cable data transmission medium comprising:

a media access controller;

a processor;

a memory;

semaphore circuitry determining which of the media access controller and the processor writes the data to the memory;

interrupt control circuitry notifying the other of the media access controller and the processor to read the data from the memory upon completion of writing; and

a bus that communicatively couples the media access controller, the processor, the semaphore circuitry, the interrupt control circuitry, and the memory.

10. The cable modem system of claim 9, further comprising a specification within a first portion of the memory, the specification governs the transfer of the data between the media access controller and the processor, one of the media access controller and the processor writes the data to a second portion of the memory.

11. The modem system of claim 9 wherein the media access controller further comprises a configurable message processor.

12. The modem system of claim 9 wherein the media access controller further comprises a message processor that is configured according to the specification.

13. The modem system of claim 9 wherein the interrupt control circuitry further comprises interrupt control logic that determines when one of the media access controller and the processor has completed writing to the memory and generates an interrupt to the other of the media access controller and the processor.

14. The modem system of claim 13 wherein the interrupt is an inter-processor interrupt.

15. The modem system of claim 13 wherein the processor is a control processor of the cable modem system.

16. The modem system of claim 9 wherein the interrupt control circuitry further comprises:

an interrupt control status register; and

interrupt control logic that determines when one of the media access controller and the processor has completed writing to the memory based on the status of the interrupt control status register.

17. A cable modem system for providing an external system access to a cable data transmission medium comprising:

a media access controller;

a control processor;

a memory coupled to the media access controller and the control processor, one of the media access controller and the control processor writing to the memory; and

interrupt control circuitry coupled to the media access controller and the control processor, the interrupt control circuitry notifying the other of the media access controller and the control processor to read the data from the memory upon completion of writing.

18. The modem system of claim 17 wherein the media access controller is configurable according to a specification.

19. The modem system of claim 17 wherein the interrupt control circuitry generates an inter-processor interrupt upon the completion of writing.