Adaptable configuration interface for a programmable logic device

• US 6,665,766 B1
• Filed: 08/14/2000
• Issued: 12/16/2003
• Est. Priority Date: 08/14/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Sundararajan, Prasanna, Guccione, Steven A.
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/639,513
• Time in Patent Office: 1,219 Days
• Field of Search: 710/100, 710/305-315, 710/104, 710/10, 716/16, 716/17, 365/201, 365/182, 713/1-100
• US Class Current: 710/305
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

An adaptable configuration interface for a programmable logic device (PLD). A PLD includes a plurality of configuration pins and circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD. A register that is external to the PLD is connected to the configuration pins of the PLD, and a processor is coupled to the register. A first set of routines, each executable on the processor, are configured to read and write values from and to the register. A second set of routines, each executable on the processor, provide an application programming interface for the configuration and readback of data from the PLD via the first set of routines. The layered structure of the interface routines aids in incrementally changing from a software controlled configuration interface to an interface that is a combination of hardware and software.

Claims

1. A configuration interface arrangement for a programmable logic device (PLD) having a plurality of configuration pins, the configuration pins including one or more input/output data pins, a plurality of configuration control pins including a read/write control pin, and a configuration clock pin, the PLD having circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD, the configuration interface arrangement comprising:

a register external to the PLD and including a plurality of memory elements respectively connected to the configuration pins of the PLD;

a processor coupled to the register;

a first set of routines executable on the processor and configured to read and write bit values from and to the register; and

a second set of routines executable on the processor, a first one of the second set of routines configured to write data to the PLD via calls to the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the write protocol.

2. The configuration interface arrangement of claim 1, wherein the second set of routines further includes a second routine configured to read data from the PLD via the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the read protocol.

3. The configuration interface arrangement of claim 2, wherein the first routine of the second set is configured to write a selectable quantity of configuration data to the PLD responsive to an input parameter.

4. The configuration interface arrangement of claim 3, wherein the second routine of the second set is configured to read a selectable quantity of data from the PLD responsive to an input parameter.

5. The configuration interface arrangement of claim 1, wherein the PLD includes circuitry implementing a protocol to reset the PLD, and the second set of routines further comprises a third routine configured to reset the PLD via the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the reset protocol.

6. The configuration interface arrangement of claim 2, wherein the first set of routines are adaptable for system-specific characteristics of the register, and the second set of routines are portable between processors.

7. The configuration interface arrangement of claim 6, wherein the first routine of the second set is configured to write a selectable quantity of configuration data to the PLD responsive to an input parameter.

8. The configuration interface arrangement of claim 7, wherein the second routine of the second set is configured to read a selectable quantity of data from the PLD responsive to an input parameter.

9. The configuration interface arrangement of claim 6, wherein the PLD includes circuitry implementing a protocol to reset the PLD, and the second set of routines further comprises a third routine configured to reset the PLD via the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the reset protocol.

10. A method for selectably configuring and reading back data from a programmable logic device (PLD) having a plurality of configuration pins, the configuration pins including one or more input/output data pins, a plurality of configuration control pins including a read/write control pin, and a configuration clock pin, the PLD having circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD, comprising:

connecting respective memory elements of a register external to the PLD to the configuration pins of the PLD;

providing a first set of routines executable on a processor, the first set of routines configured to read and write bit values from and to the register responsive to routine calls;

providing a second set of routines executable on the processor, a first one of the second set of routines configured to write data to the PLD via calls to the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the write protocol, and a second one of the second set of routines configured to read data from the PLD via the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the read protocol;

configuring the PLD via a routine call to the first routine; and

reading back data from the PLD via a routine call to the second routine.

11. The method of claim 10, wherein the first routine of the second set is configured to write a selectable quantity of configuration data to the PLD responsive to an input parameter.

12. The method of claim 11, wherein the second routine of the second set is configured to read a selectable quantity of data from the PLD responsive to an input parameter.