Interface controller that controls the rate at which data is transfer based on the destination address of the data

• US 6,665,810 B1
• Filed: 01/24/2000
• Issued: 12/16/2003
• Est. Priority Date: 02/08/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Sakai, Yasushi
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): CONNOLLY, MARK A
• Application Number:
  US09/490,120
• Time in Patent Office: 1,422 Days
• Field of Search: 713/600, 340/825.2, 340/825.21
• US Class Current: 713/600
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An interface controller adaptively changes the data transfer rate of data being transferred between two or more devices depending on whether one of the devices is powered by an internal power supply and on the destination of the data. The controller includes a clock generator that generates a clock signal, a transfer unit that performs one of a first data transfer and a second data transfer at a transfer rate based on the clock signal, and a control circuit for adaptively changing the frequency of the clock signal depending on whether the first or second data transfer is to be performed.

Claims

1. An interface controller performing a first data transfer with a first device, comprising:

a first port for connecting to a second device to perform a second data transfer;

a second port for connecting to a third device to perform a the second data transfer;

a clock generating circuit for generating a clock signal having a frequency;

a transfer unit, connected to the clock generating circuit, for performing one of the first data transfer and the second data transfer; and

a clock control unit, connected to the clock generating circuit, for performing the second data transfer when data is addressed to one of the second device and the third device.

2. The interface controller of claim 1, wherein the transfer unit determines whether data is addressed to the first device or to one of the second and third devices and the clock control unit determines one of the first and second data transfers to be performed based on the determination result.

3. The interface controller of claim 2, wherein the second transfer is faster than the first data transfer.

4. The interface controller of claim 3, wherein the clock control unit changes the frequency of the clock signal to a first frequency corresponding to the first data transfer when the first data transfer is performed and changes the frequency of the clock signal to a second frequency corresponding to the second data transfer when the second data transfer is performed.

5. The interface controller of claim 1, wherein the clock control unit changes the frequency of the clock signal to a first frequency corresponding to a first transfer rate when the first data transfer is performed and changes the frequency of the clock signal to a second frequency corresponding to a second transfer rate that is faster than the first transfer rate when the second data transfer is performed.

6. The interface controller of claim 1, wherein the interface controller is powered by one of an internal power supply and an external power supply, wherein when the interface controller is powered by the external power supply, the clock control unit changes the frequency of the clock signal to a first frequency corresponding to a first transfer rate for the first data transfer and changes the frequency of the clock signal to a second frequency corresponding to a second transfer rate that is faster than t he first transfer rate for the second data transfer, and wherein when the interface controller is powered by the internal power supply, the clock control unit maintains the frequency of the clock signal to the first frequency.

7. The interface controller of claim 1, wherein the interface controller is powered by one of an internal power supply and an external power supply, wherein when the interface controller is powered by the internal power supply, the clock control unit changes the frequency of the clock signal to a first frequency corresponding to a first transfer rate for the first data transfer and changes the frequency of the clock signal to a second frequency corresponding to a second transfer rate that is faster than the first transfer rate for the second data transfer, and wherein when the interface controller is powered by the external power supply, the clock control unit maintains the frequency of the clock signal to the second frequency.

8. The interface controller of claim 1, wherein the clock generating unit includes:

an oscillation circuit for generating a basic signal; and

a frequency dividing circuit, connected to the oscillation circuit, for generating the clock signal by frequency-dividing the basic signal in accordance with a predetermined frequency-dividing ratio, wherein the clock control unit changes the frequency dividing ratio between the first and second data transfers.

9. The interface controller of claim 1, wherein at the second data transfer, data is input to the first port and output from the second port.

10. The interface controller of claim 1, wherein the transfer unit reports a second transfer rate, which corresponds to the communication performance of the second device or the third device, to the second device or the third device before starting the second data transfer and reports a first transfer rate that is slower than the second transfer rate when the first data transfer is performed between the first device and one of the second and third devices.

11. The interface controller of claim 10, wherein the clock control unit sets the frequency of the clock signal to a frequency corresponding to the first transfer rate until the data for performing the second data transfer is provided to the transfer unit.

12. The interface controller of claim 1, wherein the first device is powered by an internal power supply.

13. The interface controller of claim 1, wherein the second device and the third device are powered by an external power supply.

14. An interface controller for transferring data between at least two devices connected to a bus, the controller comprising:

an I/O port connected to the bus for sending and receiving data;

an interface circuit, connected to the I/O port, for passing data to and from the I/O port at one of the first data transfer rate, which is determined by a first clock signal, and a second data transfer rate, which is determined by a second clock signal;

an internal port, connected to the interface circuit, being set to transfer data at the first data transfer rate;

a clock signal generator, connected to the interface circuit, for generating the first clock signal and the second clock signal; and

a control circuit, connected to the clock signal generator, for generating a first control signal used to generate the first clock signal when data is addressed to the interface controller and generating a second control signal used to generate the second clock signal when data is addressed to one of the at least two devices.

15. The interface controller of claim 14, wherein the I/O port includes a first I/O port connectable to a first device and a second I/O port connectable to a second device.

16. The interface controller of claim 15, wherein the clock signal generator comprises:

an oscillator for generating an oscillation signal; and

a frequency dividing circuit, connected to the oscillator, for receiving the oscillation signal, the frequency dividing circuit generating the first and second clock signals using the oscillation signal, wherein the frequency dividing circuit generates one of the first and second clock signals using a frequency dividing ratio specified by the corresponding one of the first and second control signals.

17. The interface controller of claim 16, wherein the control circuit includes a power supply decision circuit for selecting a first frequency dividing ratio specified by the first control signal when power is supplied to the controller from an external power source and a second frequency dividing ratio specified by the second control signal when the power is supplied to the controller from an internal power source.

18. The interface controller of claim 17, wherein the control circuit includes a self device decision circuit for setting one of the first and second control signals based on a destination of the received data.

19. The interface controller of claim 14, wherein the bus comprises an IEEE 1395 type bus.

20. The interface controller of claim 14, further comprising a buffer circuit, connected to the interface circuit, for storing the data received from the I/O port and for storing internally generated data.

21. A method for transferring data between a self device performing a first data transfer and a plurality of other devices performing a second data transfer, comprising the steps of:

determining whether the data to be transferred is addressed to the self device or to one of the other devices;

performing the first data transfer between the self device and one of the other devices at a first transfer rate when the data is addressed to the self device; and

performing the second data transfer between a first other device and a second other device via the self device at a second transfer rate that is faster than the first transfer rate when the data is addressed to one of the other devices.

22. A method for transferring data between a self device and a plurality of other devices, wherein the self device is powered by an internal power supply, the method comprising the steps of:

determining whether the data to be transferred is addressed to the self device or to one of the other devices;

performing a first data transfer between the self device and one of the other devices at a first transfer rate when the data is addressed to the self device; and

performing a second data transfer between a first other device and a second other device via the self device at a second transfer rate that is faster than the first transfer rate when the data is addressed to one of the other devices.

23. A method for transferring data between a self device and at least two other devices, wherein the self device is powered by an internal power supply and the at least two devices are powered by an external power supply, the method comprising the steps of:

determining whether the data to be transferred is addressed to the self device or to one of the at least two devices;

performing the first data transfer between the self device and one of the at least two other devices at a first transfer rate when the data is addressed to the self device; and

performing a second data transfer between a first other device and a second other device via the self device at a second transfer rate when the data is addressed to one of the at least two other devices.