Apparatus and method for implementing a wireless system-on-a-chip with a reprogrammable tester, debugger, and bus monitor

• US 6,665,817 B1
• Filed: 05/05/2000
• Issued: 12/16/2003
• Est. Priority Date: 05/07/1999
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: MorphICs Technology, Inc. (Infineon Technologies AG)
• Inventors: Rieken, Keith
• Primary Examiner(s): BADERMAN, SCOTT T
• Application Number:
  US09/565,688
• Time in Patent Office: 1,320 Days
• Field of Search: 714/30-726, 714/729, 714/733-734
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements

Abstract

A wireless communication system-on-a-chip comprises a system bus, a set of fixed function processors connected to the system bus, an embedded processor connected to the system bus, and reconfigurable logic connected to the system bus. The reconfigurable logic supports an operational mode and a diagnostic mode. In the operational mode, the system operates to support different air interface protocols and data rates. In the diagnostic mode, the system alternately tests the system, debugs the system, and monitors bus activity within the system.

Claims

1. A reconfigurable controller, comprising:

a configuration and test controller; and

reconfigurable logic connected to said configuration and test controller, wherein said reconfigurable logic is configured to perform bus emulation operations in one mode, and is reconfigured to perform at least one of the functions selected from a group consisting of hardware testing operations, software debugging operations, and bus monitoring operations in another mode.

2. The reconfigurable controller of claim 1 wherein said configuration and test controller includes a Joint Test Access Group (JTAG) interface.

3. The reconfigurable controller of claim 1 wherein said bus emulation operations include at least one function selected from a group consisting of emulating temporary applications, fault insertion, transaction initiation, transaction responding, emulating as a bus master and emulating as a bus slave.

4. The reconfigurable controller of claim 1 wherein said hardware testing operations include at least one function selected from a group consisting of Random Access Memory Built In Self Test (RAM BIST), Logic Built In Self Test (Logic BIST), Boundary Scan Chain (BSC), Automatic Test Pattern Generation (ATPG) and Signature Analysis testing.

5. The reconfigurable controller of claim 1 wherein said software debugging operations include at least one function selected from a group consisting of single stepping, instruction insertion, breakpoint insertion, monitoring and reporting specified events occurring in connection with fixed logic blocks and static devices.

6. The reconfigurable controller of claim 1 wherein said bus monitoring operations include run-time bus monitoring and user-defined monitoring functions.

7. The reconfigurable controller of claim 1 wherein the controller resides within a target system under testing.

8. A reconfigurable controller, comprising:

a configuration and test controller; and

a reconfigurable logic connected to said configuration and test controller, said reconfigurable logic supporting testing operations in a first mode, debugging operations in a second mode, and bus monitoring operations in a third mode, wherein said reconfigurable logic supports a bus emulator function during said third mode.

9. A reconfigurable controller, comprising:

a bus;

a set of fixed function processors coupled to said bus;

a configuration and test controller; and

reconfigurable logic connected to said configuration and test controller, said reconfigurable logic supporting testing operations in a first mode, debugging operations in a second mode, and bus monitoring operations in a third mode.

10. The reconfigurable controller of claim 9, wherein said set of fixed function processors support baseband processing.

11. The reconfigurable controller of claim 9, further comprising serial scan chains to provide run-time configuration, alternative algorithm selection, and run-time debug for a fixed function processor of said set of fixed function processors.

12. The reconfigurable controller of claim 9, further comprising configuration registers for parameterizing a fixed function processor of said set of fixed function processors.

13. The reconfigurable controller of claim 12, wherein said configuration registers are programmable after reset using scan chain logic.

14. A reconfigurable controller, comprising:

a configuration and test controller; and

reconfigurable logic connected to said configuration and test controller, said reconfigurable logic supporting testing operations in a first mode, debugging operations in a second mode, and bus monitoring operations in a third mode, wherein said reconfigurable logic further supports an operational mode for different air interface protocols and data rates.

15. A method for operating a reconfigurable controller, comprising:

configuring reprogrammable logic of the reconfigurable controller for performing the function of bus emulation in one mode; and

reconfiguring said reprogrammable logic for performing at least one of the functions selected from a group consisting of hardware testing operations, software debugging operations, and bus monitoring operations in another mode.

16. The method of claim 15, wherein said configuration controller includes a Joint Test Access Group (JTAG) interface.

17. The method of claim 15, wherein said step of performing the function of bus emulation includes at least one function selected from a group consisting of emulating temporary applications, fault insertion, transaction initiation, transaction responding, emulating as a bus master and emulating as a bus slave.

18. The method of claim 15, wherein said step of performing the function of hardware testing operations includes at least one function selected from a group consisting of Random Access Memory Built In Self Test (RAM BIST), Logic Built In Self Test (Logic BIST), Boundary Scan Chain (BSC), Automatic Test Pattern Generation (ATPG) and Signature Analysis testing.

19. The method of claim 15, wherein said step of performing the function of software debugging operations includes at least one function selected from a group consisting of single stepping, instruction insertion, breakpoint insertion, monitoring and reporting specified events occurring in connection with fixed logic blocks and static devices.

20. The method of claim 15, wherein said step of performing the function of bus monitoring operations includes run-time bus monitoring and user-defined monitoring functions.

21. The method of claim 15 wherein said reconfigurable controller resides within a target system under testing.