Method and apparatus for monitoring component latency drifts

• US 6,665,823 B2
• Filed: 01/25/2002
• Issued: 12/16/2003
• Est. Priority Date: 03/18/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Terry R.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Bonzo, Bryce P
• Application Number:
  US10/054,909
• Publication Number:
  US 20020129302A1
• Time in Patent Office: 690 Days
• Field of Search: 714/56, 714/55, 714/47, 713/400, 713/401, 710/58, 710/60
• US Class Current: 714/55
• CPC Class Codes: G06F 11/24 Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such as SLDRAMs, that have programmable response times. A response time monitoring circuit in the form of a phase detector includes a plurality of flip-flops with the data inputs commonly connected to receive a response ready signal from a component, such as a memory circuit, in response to a command to perform a task. Each clock input of the flip-flop is connected to a clock signal at a different phase of a response period. The outputs of the flip-flops determine the phase at which the response ready signal was generated by the component.

Claims

1. An apparatus for monitoring the latency of a component that generates a ready signal after completing an assigned task, the apparatus comprising:

control logic adapted to interface with the component; and

a response time measurement circuit connected to the control logic and the component, the response time measurement circuit receiving, concurrently at a plurality of inputs, said ready signal of a component whose response time is being measured after said component has completed an assigned task, said response time measurement circuit utilizing said ready signal received concurrently at said plurality of inputs and a plurality of delayed clock signals to provide a measured response time to the control logic based upon the received ready signal.

2. The apparatus of claim 1, wherein the response time measurement circuit comprises a phase detector.

3. The apparatus of claim 2, wherein the phase detector comprises a plurality of transparent latches each having a data input, a data output, and a clock input, the data input of each transparent latch being connected to receive said ready signal of said component whose response time is being measured and the clock input of each transparent latch being connected to receive a respective one of said delayed clock signals generated at a different point of a response window such that the data outputs of the transparent latches indicate the respective portion of the response window in which a data ready signal is received.

4. The apparatus of claim 3, wherein the transparent latches are data flip-flops.

5. The apparatus of claim 3, further comprising a logic circuit connected to the data output of at least one of the transparent latches such that the logic circuit generates an excessive latency drift signal when the data output indicates that the data ready signal has drifted in excess of a predetermined threshold.

6. A component controller comprising:

control logic adapted to interface with the component;

a response time measurement circuit connected to the control logic and the component for detecting an excessive latency drift of the component in responding to a command and providing an excessive latency drift signal to the control logic; and

a local memory connected to the control logic;

wherein the control logic is adapted to store information on the component in the local memory when an excessive latency drift signal is received, said information comprising an identification code of the component and the time at which the excessive latency drift signal is provided to the control logic.

7. The controller of claim 6, wherein the component has a programmable response time.

8. The controller of claim 6, wherein the component is a memory circuit.

9. The controller of claim 8, wherein the memory circuit is a programmable response time memory circuit.

10. The controller of claim 9, wherein the programmable response time memory circuit is an SLDRAM memory circuit.

11. The controller of claim 10, wherein the control logic is adapted to recalibrate at least one SLDRAM memory circuit upon receipt of an excessive latency drift signal from an SLDRAM memory circuit.

12. A memory controller comprising:

control logic adapted to interface with a memory component and to generate a response window signal when the memory component is commanded to retrieve data therein;

an offset clock generator connected to receive the response window signal for generating a plurality of phase clock signals;

a phase detector comprising a plurality of transparent latches each having a data input, a data output, and a clock input, the clock input of each transparent latch being connected to receive a respective phase clock signal from the offset clock generator, and the data input of each transparent latch being connected to receive a data ready signal from the memory component, the data ready signal being provided by said memory component when the data is available;

a logic circuit having an input connected to an output of the transparent latches and an output connected to the control logic for generating an excess latency drift signal; and

a local memory connected to the control logic for storing component information for a memory component which caused the excess latency drift signal to be generated.

13. The controller of claim 12, wherein the memory component is an SLDRAM and the control logic is adapted to recalibrate at least one SLDRAM memory component upon receipt of an excess latency drift signal.

14. The controller of claim 13, wherein the phase clock signals are evenly distributed over a response window initiated by said response window signal.

15. The controller of claim 14, wherein the phase clock signals are distributed over an entire response window initiated by said response window signal.

16. The controller of claim 15, wherein the response window consists of one memory clock cycle.

17. A computer system comprising:

a processor;

a memory component; and

a memory control system connected to and operative with the processor and the memory component, the memory control system comprising;

control logic adapted to communicate with the memory component;

a response time measurement circuit connected to the control logic and the component for detecting an excessive latency drift of the component in responding to a command and providing an excessive latency drift signal to the control logic; and

a local memory connected to the control logic;

wherein the control logic is adapted to store information on the component in the local memory when an excessive latency drift signal is received, said component information comprising an identification code of the component and the time at which the excessive latency drift signal is provided to the control logic.

18. The controller of claim 17, wherein the component is a memory circuit.

19. The controller of claim 18, wherein the memory circuit is an SLDRAM memory circuit.

20. The controller of claim 19, wherein the control logic is adapted to recalibrate at least one SLDRAM memory circuit upon receipt of an excessive latency drift signal from an SLDRAM memory circuit.

21. A computer system comprising:

a processor;

a memory component; and

a memory control system connected to and operative with the processor and the memory component, the memory control system comprising;

control logic adapted to interface with a memory component and to provide a response window signal at the start of a response window;

an offset clock generator connected to receive the response window signal for generating a plurality of phase clock signals;

a phase detector comprising a plurality of transparent latches each having a data input, a data output, and a clock input, the clock input of each transparent latch being connected to receive a respective phase clock signal from the offset clock generator, and the data input of each transparent latch being connected to receive a data ready signal from the memory component;

a logic circuit having an input connected to a data output of at least one of the transparent latches and an output connected to the control logic for generating an excess latency drift signal; and

a local memory connected to the control logic;

wherein the control logic is adapted to store information pertaining to the component causing the excess latency drift signal to be generated.

22. The controller of claim 21, wherein the memory component is a programmable response time memory component and the control logic is adapted to recalibrate at least one programmable response time memory component upon receipt of an excess latency drift signal.

23. The controller of claim 22, wherein the phase clock signals are evenly distributed over a response window initiated by said response window signal.

24. The controller of claim 23, wherein the phase clock signals are distributed over an entire response window initiated by said response window signal.

25. The controller of claim 24, wherein the response window consists of one memory clock cycle.

26. A component controller comprising:

control logic adapted to interface with the component;

a response time measurement circuit connected to the control logic and the component for detecting an excessive latency drift and providing an excessive latency drift signal to the control logic; and

a local memory connected to the control logic;

wherein the control logic is adapted to store information on the component in the local memory when an excessive latency drift signal is received and to determine when the latency drift of component indicates that the component may need replacing or relocation.

27. The controller of claim 26, wherein the control logic determines that the component may need replacing or relocating by calculating short and long term averages of the time between excessive latency drifts and comparing the ratio of the averages to a predetermined threshold.

28. The controller of claim 26, wherein the control logic determines that the component may need replacing or relocating by calculating short and long term averages of the magnitude of the latency drifts and comparing the ratio of the averages to a predetermined threshold.

29. The controller of claim 26, wherein the control logic determines that the component may need replacing or relocating by calculating the standard deviation of the time between excessive latency drifts, counting a total number of latency drifts whose drift time is below a first predetermined threshold based on the standard deviation;

and comparing the total to a second predetermined threshold.

30. The controller of claim 26, wherein the control logic determines that the component may need replacing or relocating by calculating the standard deviation of the latency drift of the component, counting the total of the number of latency drifts that exceed a first predetermined threshold based on the standard deviation, and comparing the total to a second predetermined threshold.

31. A memory circuit controller comprising:

control logic adapted to interface with a plurality of memory circuits;

a response time measurement circuit connected to the control logic and the memory circuits for detecting an excessive latency drift and providing an excessive latency drift signal to the control logic;

a local memory connected to the control logic;

wherein the control logic is adapted to store failure information in the local memory when an excessive latency drift signal is received; and

wherein the control logic is further adapted to determine when the latency drift of one memory circuit indicates that the one memory circuit may need replacing or relocating by calculating the ratio of excessive latency drifts caused by the one memory circuit to the total number of latency drifts, and comparing the ratio to a predetermined threshold.

32. A computer system comprising:

a processor;

an output device connected to the processor;

a memory component; and

a memory control system connected to and operative with the processor and the memory component, the memory control system comprising;

control logic adapted to interface with the memory component;

a response time measurement circuit connected to the control logic and the component for detecting an excessive latency drift and providing an excessive latency drift signal to the control logic; and

a local memory connected to the control logic;

wherein the control logic is adapted to store information on the component in the local memory when an excessive latency drift signal is received, to determine when the latency drift of the component indicates that the component may need replacing or relocating and to send a message to the processor indicating which component may need replacing or relocating, and wherein the processor outputs the message to the output device.

33. The computer system of claim 32, wherein the control logic determines that the component may need replacing or relocating by calculating short and long term averages of the time between excessive latency drifts and comparing the ratio of the averages to a predetermined threshold.

34. The computer system of claim 32, wherein the control logic determines that the component may need replacing or relocating by calculating short and long term averages of the magnitude of the latency drifts and comparing the ratio of the averages to a predetermined threshold.

35. The computer system of claim 32, wherein the control logic determines that the component may need replacing or relocating by calculating the standard deviation of the time between excessive latency drifts, counting a total number of latency drifts whose drift time is below a first predetermined threshold based on the standard deviation;

and comparing the total to a second predetermined threshold.

36. The computer system of claim 32, wherein the control logic determines that the component may need replacing or relocating by calculating the standard deviation of the latency drift of the component, counting the total of the number of latency drifts that exceed a first predetermined threshold based on the standard deviation, and comparing the total to a second predetermined threshold.

37. A computer system comprising:

a processor;

an output device connected to the processor;

a plurality of memory components; and

a memory control system connected to and operative with the processor and the memory components, the memory control system comprising;

control logic adapted to interface with the memory components;

a response time measurement circuit connected to the control logic and the memory components for detecting an excessive latency drift and providing an excessive latency drift signal to the control logic;

a local memory connected to the control logic;

wherein the control logic is adapted to store failure information in the local memory when an excessive latency drift signal is received; and

wherein the control logic is further adapted to determine when the latency drift of one component indicates that the one component may need replacing or relocating by calculating the ratio of excessive latency drifts caused by the one component to the total number of latency drifts, and comparing the ratio to a predetermined threshold.

38. A method for monitoring latency drift of a component which generates a ready signal after completing an assigned task, comprising the steps of:

providing a plurality of transparent latches, each of the latches having a data input, a data output, and a clock input;

connecting the data input of each transparent latch to receive a ready signal of a component whose response time is being measured;

connecting the clock input of each transparent latch to receive a respective clock signal generated at a different point of a response window such that the data outputs of the transparent latches indicate the respective portion of the response window in which a data ready signal is received; and

detecting the respective data outputs of the transparent latches.

39. The method of claim 38, wherein the clock signals are distributed over the entire response window.

40. The method of claim 38, wherein the clock signals are evenly distributed.

41. The method of claim 38, wherein the response window consists of one clock cycle.

42. The method of claim 38, further comprising the step of connecting a logic circuit to the data output of at least one transparent latch to generate an excessive latency drift signal.

43. A method for monitoring latency drift of a programmable response time memory component which generates a ready signal after completing a data retrieval operation, comprising the steps of:

providing a plurality of transparent latches, each of the latches having a data input, a data output, and a clock input;

connecting the data input of each transparent latch to receive a ready signal of a programmable response time memory component whose response time is being measured;

connecting the clock input of each transparent latch to receive a respective clock signal generated at a different point of a response window such that the data outputs of the transparent latches indicate the respective portion of the response window in which a data ready signal is received;

connecting a logic circuit to the data output of at least one transparent latch to generate an excessive latency drift signal;

observing the respective data outputs of the transparent latches to determine a latency drift when an excessive latency drift signal is received;

comparing the determined latency drift to a predetermined threshold; and

recalibrating at least one programmable response time memory component when the determined latency drift exceeds the predetermined threshold.

44. The method of claim 43, wherein the programmable response time memory component is an SLDRAM.

45. A method of determining when a component may need to be replaced comprising the steps of:

monitoring latency drifts of a component;

storing component latency drift information;

comparing the stored latency drift information to a predetermined threshold; and

indicating a need for replacement when the stored latency drift information exceeds the threshold.

46. The method of claim 45, wherein the step of comparing the stored latency drift information to a predetermined threshold comprises:

calculating a short term average of the time between excessive latency drifts,

calculating a long term average of the time between excessive latency drifts; and

comparing the ratio of the averages to a predetermined threshold.

47. The method of claim 45, wherein the step of comparing the stored latency drift information to a predetermined threshold comprises:

calculating a short term average of the magnitude of the latency drifts,

calculating a long term average of the magnitude of the latency drifts; and

comparing the ratio of the averages to a predetermined threshold.

48. The method of claim 45, wherein the step of comparing the stored latency drift information to a predetermined threshold comprises:

calculating a standard deviation of the time between excessive latency drifts;

counting a total of the number of latency drifts whose drift time is below a first predetermined threshold based on the standard deviation; and

comparing the total to a second predetermined threshold.

49. The method of claim 45, wherein the step of comparing the stored latency drift information to a predetermined threshold comprises:

calculating a standard deviation of the magnitude of the stored latency drifts;

counting a total of the number of latency drifts whose magnitude exceeds a first predetermined threshold based on the standard deviation; and

comparing the total to a second predetermined threshold.

50. An apparatus for monitoring the latency of a component that generates a ready signal after completing an assigned task, the apparatus comprising:

control logic adapted to interface with the component; and

a response time measurement circuit, including a plurality of transparent latches, connected to the control logic and the component, each latch of said plurality concurrently receiving said ready signal of a component whose response time is being measured after said component has completed an assigned task, said response time measurement circuit providing a measured response time to the control logic based upon the received ready signal.