Method and arrangement for rapid silicon prototyping

• US 6,665,855 B2
• Filed: 12/11/2001
• Issued: 12/16/2003
• Est. Priority Date: 12/18/1998
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Pontius, Timothy, Bapst, Mark, Payne, Robert
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US10/016,731
• Publication Number:
  US 20030204831A1
• Time in Patent Office: 735 Days
• Field of Search: 716/1-18, 710/56, 710/100, 710/128, 710/129, 710/62
• US Class Current: 716/104
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing

Abstract

A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Claims

1. A method for designing a semiconductor circuit arrangement, comprising:

providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros;

using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform; and

extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference-chip development platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software.

2. A method, according to claim 1, wherein the programmable circuit includes at least one of:

a FPGA device;

a FPGA plug-in board;

an expansion board; and

an external circuit communicatively coupling via the extended deconfigurable and extendible reference-chip development platform.

3. A method for designing a semiconductor circuit arrangement comprising:

providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros;

using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform and synthesizing a subset of the collection of functional block macros to the programmable circuit; and

extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference chip development, platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software.

4. A method, according to claim 3, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros.

5. A method, according to claim 4, wherein said at least one reused functional block macro is reused from HDL code into the programmable circuit.

6. A method, according claim 3, wherein at least one of the functional block macros in the subset is used from a functional block macro obtained from the deconfigurable and extendible reference-chip development platform and reused by retargeting to an ASIC that developed from the hardware representation.

7. A method, according to claim 6, further including modifying the subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

8. A method, according to claim 3, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros, and further including modifying the subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

9. A method for designing a semiconductor circuit arrangement, comprising:

providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros;

using a collection of functional block macros at one of which is obtained from the deconfigurable and extendible reference-chip development platform;

extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference-chip development platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software; and

validating a hardware representation of a synthesized subset of functional block macros in the programmable circuit within the extended deconfigurable and extendible reference-chip development platform.

10. A method, according to claim 9, wherein said validating includes using at least one external device communicatively coupled with the reference-chip development platform.

11. A method, for designing a semiconductor circuit arrangement, comprising:

providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros;

using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform;

extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference-chip development platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software; and

modifying a subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

12. A method, according to claim 11, wherein the programmable circuit is hardware reconfigurable and wherein synthesizing the subset of the functional block macros to the programmable circuit includes reconfiguring the programmable circuit.

13. A system for designing a semiconductor circuit arrangement, comprising:

deconfigurable and extendible means, including a programmable circuit and a plurality of functional block macros, for developing a reference-chip;

means for using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible means; and

means for extending the deconfigurable and extendible means, including means for communicatively coupling at least one external device with the deconfigurable and extendible means, and therein providing an extended deconfigurable and extendible means that enables co-development and co-validation of hardware and software.

14. A system, according to claim 13, further including means for synthesizing a subset of the collection of functional block macros to the programmable circuit.

15. A system, according to claim 14, wherein the programmable circuit is hardware reconfigurable and wherein means for synthesizing the subset of the functional block macros to the programmable circuit is adapted to reconfigure the programmable circuit.

16. A system, according to claim 13, wherein the programmable circuit includes at least one of:

an FPGA device;

an FPGA plug-in board;

an expansion board; and

an external circuit communicatively coupling via the extended deconfigurable and extendible means.

17. A system, according to claim 13, wherein at least one of the functional block macros in the subset is reused from the collection of functional block macros.

18. A system, according to claim 17, wherein said at least one reused functional block macro is reused from HDL code into the programmable circuit.

19. A system, for designing a semiconductor circuit arrangement comprising:

deconfigurable and extendible means, including a programmable circuit and a plurality of functional block macros for developing a reference-chip;

means for using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible means;

means for extending the deconfigurable and extendible means, including means for communicatively coupling at least one external device with the deconfigurable and extendible means, and therein providing an extended deconfigurable and extendible means that enables co-development and co-validation of hardware and software; and

means for validating a hardware representation of a synthesized subset of functional block macros in the programmable circuit within the extended deconfigurable and extendible means.

20. A system, according to claim 19, wherein the means for synthesizing a subset of the collection of functional block macros to the programmable circuit and at least one of the deconfigurable and extendible means and the extended deconfigurable and extendible means, are adapted to modify the subset of the functional block macros and to synthesize the subset of the functional block macros, as modified, to the programmable circuit.