Trenched gate metal oxide semiconductor device and method

• US 6,667,227 B1
• Filed: 05/17/2000
• Issued: 12/23/2003
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Liu, Yowjuang W., Wollesen, Donald L.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): RICHARDS, NORMAN DREW
• Application Number:
  US09/574,695
• Time in Patent Office: 1,315 Days
• Field of Search: 438/197, 438/270, 438/282, 438/585, 438/589, 438/592
• US Class Current: 438/589
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

Claims

1. A method for fabricating a semiconductor device with a trenched gate electrode comprising:

etching a semiconductor substrate to form a trench having substantially upright vertical surfaces and a bottom surface in the semiconductor substrate;

forming a trench-to-gate dielectric layer on the substantially vertical surfaces and the bottom surface inside the trench;

forming a trenched gate electrode inside the trench by depositing a polysilicon layer;

selectively removing the polysilicon layer to form the trenched gate electrode and a residual polysilicon interconnect to another trenched gate electrode;

forming a source region and a drain region in the semiconductor substrate, the source and drain regions being spaced apart by the trench immediately contiguous to the substantially upright vertical sides of the trench; and

implanting a channel region formed beneath the bottom of the trench and immediately contiguous to the source region and the drain region.

2. The method of claim 1 wherein forming the trenched gate electrode further comprises

planarizing the layer of polysilicon to substantially planar orientation with a top surface of the semiconductor substrate.

3. The method of claim 1 wherein forming the trenched gate electrode further comprises

depositing and patterning a layer of photoresist on the layer of polysilicon to define the trenched gate electrode and the interconnect.

4. The method of claim 1 wherein forming the trenched gate electrode further comprises:

forming a layer of tungsten silicide on the layer of polysilicon;

depositing and patterning a layer of photoresist on the layer of tungsten silicide; and

etching the layer of tungsten silicide to form the trenched gate electrode.