Wet-etching method and method for manufacturing semiconductor device

• US 6,667,246 B2
• Filed: 12/04/2002
• Issued: 12/23/2003
• Est. Priority Date: 12/04/2001
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Mitsuhashi, Riichiro, Hayashi, Shigenori, Kubota, Masafumi
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US10/309,038
• Publication Number:
  US 20030104706A1
• Time in Patent Office: 384 Days
• Field of Search: 438/287, 438/758, 438/769, 438/770, 438/775, 438/785, 438/591, 438/778, 438/784, 438/756, 257/295, 257/310, 257/311, 257/410
• US Class Current: 438/756
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A substrate with a metal oxide film deposited thereon is annealed, and then the surface of the metal oxide film is exposed to a plasma, after which the metal oxide film is removed by wet-etching.

Claims

1. A wet-etching method, comprising:

a first step of annealing a substrate with a metal oxide film deposited thereon;

a second step of exposing a surface of the annealed metal oxide film to a plasma; and

a third step of removing, by wet-etching, at least a surface portion of the metal oxide film, which has been exposed to the plasma.

2. The wet-etching method of claim 1, wherein the second step includes a step of applying a bias power to the substrate.

3. The wet-etching method of claim 1, wherein the plasma is a plasma made of an HBr-containing gas.

4. The wet-etching method of claim 1, wherein the third step is performed by using a fluorine-containing solution.

5. The wet-etching method of claim 1, wherein the metal oxide film is an oxide film containing at least one of hafnium, zirconium, lanthanum, tantalum and aluminum.

6. A method for manufacturing a semiconductor device, comprising:

a first step of annealing a substrate with a metal oxide film deposited thereon;

a second step of depositing a conductive film on the annealed metal oxide film;

a third step of patterning the conductive film so as to form a gate electrode while exposing a portion of the metal oxide film that is located outside the gate electrode;

a fourth step of exposing a surface of the exposed portion of the metal oxide film to a plasma; and

a fifth step of removing, by wet-etching, the exposed portion of the metal oxide film, which has been exposed to the plasma.

7. The method for manufacturing a semiconductor device of claim 6, wherein the third step includes a step of successively plasma-etching the conductive film and the metal oxide film by using a mask pattern that covers a gate electrode formation region so as to thin the portion of the metal oxide film that is located outside the gate electrode.

8. A method for manufacturing a semiconductor device, comprising:

a first step of forming a dummy gate electrode on a substrate;

a second step of forming an insulative sidewall on a side surface of the dummy gate electrode;

a third step of forming an interlayer insulating film on the substrate, on which the dummy gate electrode and the sidewall have been formed, so that an upper surface of the dummy gate electrode is exposed;

a fourth step of removing the dummy gate electrode so as to form a recess in the interlayer insulating film with the sidewall being a wall surface of the recess;

a fifth step of depositing a metal oxide film on the interlayer insulating film so that the recess is partly filled;

a sixth step of annealing the substrate with the metal oxide film deposited thereon;

a seventh step of depositing a conductive film on the annealed metal oxide film so that the recess is completely filled;

an eighth step of removing a portion of the conductive film that is located outside the recess so as to form a gate electrode in the recess while exposing a portion of the metal oxide film that is located outside the recess;

a ninth step of exposing a surface of the exposed portion of the metal oxide film to a plasma; and

a tenth step of removing, by wet-etching, the exposed portion of the metal oxide film, which has been exposed to the plasma.

9. The method for manufacturing a semiconductor device of claim 8, wherein:

the first step includes a step of forming a dummy gate insulating film between the substrate and the dummy gate electrode; and

the fourth step includes a step of removing the dummy gate insulating film.

10. The method for manufacturing a semiconductor device of claim 8, wherein the ninth step includes a step of plasma-etching the exposed portion of the metal oxide film so as to thin the exposed portion of the metal oxide film.