High breakdown voltage semiconductor device

• US 6,667,515 B2
• Filed: 01/24/2002
• Issued: 12/23/2003
• Est. Priority Date: 01/26/2001
• Status: Expired due to Term

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Inoue, Tomoki
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Thinh T.
• Application Number:
  US10/053,660
• Publication Number:
  US 20020100935A1
• Time in Patent Office: 698 Days
• Field of Search: 257/341, 257/484, 257/139, 257/492, 257/397, 257/481, 257/475, 357/15
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A high breakdown voltage semiconductor device includes an active area and a surrounding region. In the active area, a second semiconductor layer of a second conductivity type is formed in a first semiconductor layer of a first conductivity type. A third semiconductor layer of the first conductivity type is formed in the second semiconductor layer. A gate electrode faces through a gate insulating film the second semiconductor layer. A first main electrode is connected to the second and third semiconductor layers. A ring layer of the second conductivity type surrounds the active area at a position in the surrounding region. A first low-resistivity layer is formed in the ring layer and has a resistivity lower than that of the ring layer. The first low-resistivity layer is connected to the first main electrode.

Claims

1. A high breakdown voltage semiconductor device including an active area, and a surrounding region surrounding the active area, comprising:

a first semiconductor layer of a first conductivity type disposed as a semiconductor active layer common to the active area and the surrounding region, the first semiconductor layer having first and second main surfaces opposite to each other;

a second semiconductor layer of a second conductivity type formed in the first main surface of the first semiconductor layer in the active area;

a third semiconductor layer of the first conductivity type formed in a surface of the second semiconductor layer;

a fourth semiconductor layer disposed on or in the second main surface of the first semiconductor layer in the active area;

a gate electrode facing, through a gate insulating film, a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer;

a first main electrode electrically connected to the second semiconductor layer and the third semiconductor layer;

a second main electrode electrically connected to the fourth semiconductor layer;

a ring layer of the second conductivity type formed in the first main surface of the first semiconductor layer and surrounding the active area at a position in the surrounding region adjacent to the active area;

a first low-resistivity layer formed in a surface of the ring layer and having a resistivity lower than that of the ring layer, the first low-resistivity layer comprising a metal or polycrystalline silicon of the second conductivity type and having a resistivity of from 1×

10<sup>−

6</sup> to 1×

10<sup>−

3</sup> Ω

cm; and

a connection electrode electrically connecting the first low-resistivity layer to the first main electrode.

2. A device according to claim 1, wherein the first low-resistivity layer is disposed on the active area side relative to a center of the ring layer.

3. A device according to claim 1, wherein the first low-resistivity layer has a depth of from 0.5 to 8 μ

m.

4. A device according to claim 1, wherein the first low-resistivity layer in disposed in a trench formed in the ring layer, and the first low-resistivity layer and the connection electrode comprise a metal layer integral with the first main electrode.

5. A device according to claim 1, further comprising a second low-resistivity layer formed in a surface of the second semiconductor layer and having a resistivity lower than that of the second semiconductor layer, the second low-resistivity layer being disposed in contact with the first main electrode and the second and third semiconductor layers.

6. A device according to claim 5, wherein the first and second low-resistivity layers consist essentially of substantially the same material.

7. A device according to claim 6, wherein the first and second low-resistivity layers are disposed in trenches formed in the ring layer and the second semiconductor layer, respectively.

8. A device according to claim 7, wherein the first and second low-resistivity layers are derived from a conductive film common to the first main electrode.

9. A device according to claim 8, wherein the trenches accommodating the first and second low-resistivity layers have substantially the same depth.

10. A device according to claim 1, wherein the gate insulating film comprises first and second portions formed on the second and first semiconductor layers, respectively, the second portion being thicker than the first portion.

11. A device according to claim 1, wherein the gate insulating film and the gate electrode are buried in a trench formed in the first semiconductor layer.

12. A device according to claim 11, wherein the gate electrode comprises a plurality of gate electrode portions respectively buried in a plurality of trench portions, which are formed in the first semiconductor layer with a gap therebetween, and the gap between the trench portions forms a current passageway narrow enough to increase resistance against flow of carriers of the second conductivity type from the first semiconductor layer toward the first main electrode in an ON-state of the IGBT, thereby increasing ability to inject carriers of the first conductivity type from the third semiconductor layer into the first semiconductor layer.

13. A device according to claim 12, further comprising a dummy gap portion formed of a semiconductor layer portion between two of the trench portions and out of contact with the first main electrode.

14. A device according to claim 1, wherein the fourth semiconductor layer is of the second conductivity type.

15. A device according to claim 1, wherein the fourth semiconductor layer is of the first conductivity type and has a carrier impurity concentration higher than that of the first semiconductor layer.

16. A device according to claim 1, wherein the active area comprises a plurality of active area portions juxtaposed on the first semiconductor layer, and the surrounding region surrounds each of the active area portions.

17. A device according to claim 1, wherein the surrounding region is a junction-termination region disposed along a peripheral edge of the first semiconductor layer.

18. A device according to claim 17, further comprising an end layer of the first conductivity type formed in the first main surface of the first semiconductor layer along a peripheral edge of the first semiconductor layer, the end layer having a carrier impurity concentration higher than that of the first semiconductor layer.

19. A device according to claim 18, further comprising a third low-resistivity layer formed in a surface of the end layer and having a resistivity lower than that of the end layer.

20. A device according to claim 19, wherein the first and third low-resistivity layers consist essentially of substantially the same material.

21. A device according to claim 20, wherein the first and third low-resistivity layers are disposed in trenches formed in the ring layer and the end layer, respectively.

22. A device according to claim 21, wherein the first and third low-resistivity layers are derived from a conductive film common to the first main electrode.

23. A device according to claim 21, wherein the trenches accommodating the first and third low-resistivity layers have substantially the same depth.

24. A device according to claim 17, further comprising a protection film covering the first main surface of the first semiconductor layer and consisting essentially of a material selected from the group consisting of insulating materials and semi-insulating materials.

25. A device according to claim 24, further comprising a conductive field plate extending on top of the protection film in the junction-termination region, the field plate being electrically connected to the first main electrode.

26. A device according to claim 17, further comprising a RESURF layer of the second conductivity type formed in the first main surface of the first semiconductor layer, disposed in contact with the ring layer, and extending in the junction-termination region, the RESURF layer having a carrier impurity concentration lower than that of the ring layer.

27. A device according to claim 17, further comprising a guard ring layer of the second conductivity type formed in the first main surface of the first semiconductor layer in the junction termination region.

28. A device according to claim 27, further comprising a fourth low-resistivity layer formed in a surface of the guard ring layer and having a resistivity lower than that of the guard ring layer.

29. A device according to claim 28, wherein the first and fourth low-resistivity layers consist essentially of substantially the same material.

30. A device according to claim 29, wherein the first and fourth low-resistivity layers are disposed in trenches formed in the ring layer and the guard ring layer, respectively.

31. A device according to claim 30, wherein the first and fourth low-resistivity layers are derived from a conductive film common to the first main electrode.

32. A device according to claim 30, wherein the trenches accommodating the first and fourth low-resistivity layers have substantially the same depth.

33. A high breakdown voltage semiconductor device including an active area, and a junction-termination region surrounding the active area, comprising:

a first semiconductor layer of a first conductivity type disposed as a semiconductor active layer common to the active area and the junction-termination region, the first semiconductor layer having first and second main surfaces opposite to each other;

a second semiconductor layer of a second conductivity type formed in the first main surface of the first semiconductor layer in the active area;

a third semiconductor layer of the first conductivity type formed in a surface of the second semiconductor layer;

a fourth semiconductor layer disposed on or in the second main surface of the first semiconductor layer in the active area;

a gate electrode facing, through a gate insulating film, a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer;

a first main electrode electrically connected to the second semiconductor layer and the third semiconductor layer;

a second main electrode electrically connected to the fourth semiconductor layer;

a ring layer of the second conductivity type formed in the first main surface of the first semiconductor layer and surrounding the active area at a position in the junction-termination region adjacent to the active area;

a first low-resistivity layer formed in a surface of the ring layer and having a resistivity lower than that of the ring layer, the first low-resistivity layer comprising a metal or polycrystalline silicon of the second conductivity type and having a resistivity of from 1×

10<sup>−

6</sup> to 1×

10<sup>−

3</sup> Ω

cm;

a connection electrode electrically connecting the first low-resistivity layer to the first main electrode;

a second low-resistivity layer formed in a surface of the second semiconductor layer and having a resistivity lower than that of the second semiconductor layer, the second low-resistivity layer being disposed in contact with the first main electrode and the second and third semiconductor layers, the second low-resistivity layer consisting essentially of a material the same as that of the first low-resistivity layer;

an end layer of the first conductivity type formed in the first main surface of the first semiconductor layer along a peripheral edge of the first semiconductor layer in the junction-termination region, the end layer having a carrier impurity concentration higher than that of the first semiconductor layer; and

a third low-resistivity layer formed in a surface of the end layer and having a resistivity lower than that of the end layer, the third low-resistivity layer consisting essentially of a material the same as that of the first low-resistivity layer.

34. A device according to claim 33, wherein the first, second, and third low-resistivity layers are disposed in trenches formed in the ring layer, the second semiconductor layer, and the end layer, respectively.

35. A device according to claim 34, wherein the first, second, and third low-resistivity layers are derived from a metal film common to the first main electrode.

36. A device according to claim 35, wherein the trenches accommodating the first, second, and third low-resistivity layers have substantially the same depth.

37. A device according to claim 33, further comprising a guard ring layer of the second conductivity type formed in the first main surface of the first semiconductor layer in the junction-termination region, and a fourth low-resistivity layer formed in a surface of the guard ring layer and having a resistivity lower than that of the guard ring layer.

38. A device according to claim 37, wherein the first to fourth low-resistivity layers consist essentially of substantially the same material.

39. A device according to claim 38, wherein the first to fourth low-resistivity layers are disposed in trenches formed in the ring layer, the second semiconductor layer, the end layer, and the guard ring layer, respectively.

40. A device according to claim 39, wherein the first to fourth low-resistivity layers are derived from a conductive film common to the first main electrode.

41. A device according to claim 39, wherein the trenches accommodating the first to fourth low-resistivity layers have substantially the same depth.

42. A high breakdown voltage semiconductor device including an active area, and a surrounding region surrounding the active area, comprising:

a first semiconductor layer of a first conductivity type disposed as a semiconductor active layer common to the active area and the surrounding region, the first semiconductor layer having first and second main surfaces opposite to each other;

a second semiconductor layer of a second conductivity type formed in the first main surface of the first semiconductor layer in the active area;

a third semiconductor layer of the first conductivity type formed in a surface of the second semiconductor layer;

a fourth semiconductor layer disposed on or in the second main surface of the first semiconductor layer in the active area;

a gate electrode facing, through a gate insulating film, a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer;

a first main electrode electrically connected to the second semiconductor layer and the third semiconductor layer;

a second main electrode electrically connected to the fourth semiconductor layer;

a ring layer of the second conductivity type formed in the first main surface of the first semiconductor layer and surrounding the active area at a position in the surrounding region adjacent to the active area;

a first low-resistivity layer formed in a surface of the ring layer and having a resistivity lower than that of the ring layer; and

a connection electrode electrically connecting the first low-resistivity layer to the first main electrode,

wherein the first low-resistivity layer is disposed in a trench formed in the ring layer, and the first low-resistivity layer and the connection electrode comprise a metal layer integral with the first main electrode.

43. A device according to claim 42, wherein the first low-resistivity layer has a resistivity of from 1×

10<sup>−

6</sup> to 1×

10<sup>−

3</sup> Ω

cm.

44. A device according to claim 42, wherein the first low-resistivity layer has a depth of from 0.5 to 8 μ

m.