Thin film multi-layer high Q transformer formed in a semiconductor substrate

• US 6,667,536 B2
• Filed: 10/05/2001
• Issued: 12/23/2003
• Est. Priority Date: 06/28/2001
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Chaudhry, Samir, Thomson, J. Ross, Layman, Paul Arthur, Griglione, Michelle D., Laradji, Mohamed
• Primary Examiner(s): NGUYEN, HA T
• Application Number:
  US09/972,481
• Publication Number:
  US 20030003603A1
• Time in Patent Office: 809 Days
• Field of Search: 257/531, 257/528, 257/692, 257/700, 257/758, 296/021, 336/200, 336/220
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

A thin-film multi-layer high Q transformer. To form an outer transformer winding a plurality of parallel first level metal runners are formed in a first insulating layer overlying the semiconductor substrate. A plurality of vertical conductive vias are formed in third and fourth insulating layers and in electrical communication with each end of the first level metal runners. A fourth insulating layer is disposed over the third insulating layer and additional vertical conductive vias and a fourth level metal runner are formed therein. Thus, the fourth level metal runners and the intervening vertical conductive vias connect each of the first level metal runners to form a continuously conductive structure having a generally helical shape. The inner winding of the transformer is similarly formed. A plurality of parallel second level metal runners are formed within the second insulating layer and a plurality of conductive vias and third level metal runners are formed within the third insulating layer to interconnect the plurality of second level metal runners to form a continuously conductive structure having a generally helical shape and disposed at least partially within the outer transformer winding.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate having a plurality of insulating layers and a plurality of conductive layers therebetween;

an outer coil; and

an inner coil disposed within the interior of said outer coil;

said outer coil further comprising;

a plurality of parallel first conductive strips overlying said semiconductor substrate and formed within a lower conductive layer of the semiconductor substrate;

a first stack of one or more conductive vias in electrical connection with a first end of each one of the plurality of first conductive strips;

a second stack of one or more conductive vias in electrical connection with a second end of each one of the plurality of first conductive strips; and

a plurality of parallel second conductive strips having a first end in electrical connection with the uppermost via of the first stack of one or more conductive vias, and a second end in electrical connection with the uppermost via of the second stack of one or more conductive vias, such that a second conductive strip is disposed between and interconnects two successive first conductive strips, wherein the plurality of second conductive strips are vertically spaced-apart from the plurality of first conductive strips with at least three intervening conductive layers therebetween;

said inner coil further comprising;

a plurality of parallel third conductive strips overlying said semiconductor substrate;

a third stack of one or more conductive vias in electrical connection with a first end of each one of the plurality of third conductive strips;

a fourth stack of one or more conductive vias in electrical connection with a second end of each one of the plurality of third conductive strips; and

a plurality of parallel fourth conductive strips having a first end in electrical connection with the uppermost via of the third stack of one or more conductive vias, and a second end in electrical connection with the uppermost via of the fourth stack of one or more conductive vias, such that a fourth conductive strip is disposed between and interconnects two successive third conductive strips , wherein the plurality of second conductive strips are vertically spaced-apart from the plurality of first conductive strips with at least three intervening conductive layers therebetween.

2. A multi-level integrated circuit structure, comprising:

a semiconductor substrate having a plurality of insulating layers and a plurality of conductive layers therebetween, and further having a plurality of active devices therein;

an outer winding; and

an inner winding at least partially disposed within the interior of said outer winding;

said outer winding further comprising;

runner conductive portions including first and second terminal ends of the outer winding;

vertical conductive via portions;

wherein a plurality of first lower runner portions are formed in a lower conductive layer of the semiconductor substrate;

wherein first upper runner portions are formed with at least three intervening conductive layer between the plurality of first lower runner portions and the first upper runner portions;

wherein two or more vertically aligned first via portions effect electrical connection between a first end of a first one of the plurality of first lower runner portions and an overlying first end of a first upper runner portion;

wherein two or more vertically aligned second via portions effect electrical connection between a first end of a second one of the plurality of first lower runner portions and an overlying second end of the first upper runner portion;

wherein each of the first and the second terminal ends of the outer winding is connected to one of the plurality of active devices;

said inner winding further comprising;

runner conductive portions including first and second terminal ends of the inner winding;

vertical conductive via portions;

wherein a plurality of second lower runner portions are formed in a lower conductive layer of the semiconductor substrate;

wherein second upper runner portions are formed with at least one intervening conductive layer between the plurality of second lower runner portions and the second upper runner portions;

wherein two or more vertically aligned third via portions effect electrical connection between a first end of a first one of the plurality of second lower runner portions and an overlying first end of a second t upper runner portion;

wherein two or more vertically aligned fourth via portions effect electrical connection between a first end of a second one of the plurality of second lower runner portions and an overlying second end of the second upper runner portion

wherein each of the first and second terminal ends of the inner winding is connected to one of the plurality of active devices.