Low frequency switching voltage pre-regulator

• US 6,667,602 B2
• Filed: 03/08/2002
• Issued: 12/23/2003
• Est. Priority Date: 03/08/2002
• Status: Expired due to Fees

• Current Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Original Assignee: Visteon Global Technologies Incorporated (Visteon Corporation)
• Inventors: Cook, Roger J.
• Primary Examiner(s): Patel, Rajnikant B.
• Application Number:
  US10/094,077
• Publication Number:
  US 20030169024A1
• Time in Patent Office: 655 Days
• Field of Search: 323/268, 323/272, 323/282, 323/283, 323/284, 323/266, 323/285, 363/89, 363/95, 363/81, 363/85, 363/65
• US Class Current: 323/268
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

The low-frequency, low power switching voltage switching pre-regulator is operable to propagate The pre-regulator is comprised of a chopping circuit, a pre-driver switching circuit and a feed back circuit. The output of the chopping circuit defines the output of the voltage pre-regulator and an input voltage is received at the input of the chopping circuit. The feedback circuit senses the magnitude of the voltage at the chopping circuit and derives a feedback signal in response thereto. The PWM interface circuit receives the feedback signals and a PWM signal of the type generally derived from a microprocessor. The PWM interface circuit switches the chopping circuit in response to the feedback and the PWM signals.

Claims

1. A low-frequency switching voltage pre-regulator circuit, comprising:

an input node operative to receive an input voltage signal V_IN having a magnitude substantially in the range from and including about 20 Volts to and including about 58 Volts;

a pulse width modulated (“

PWM”

) signal input node operative to receive a PWM signal having a duty cycle between approximately 25 percent and 50 percent and having a frequency substantially in the range from and including about 5 kiloHertz to and including about 15 kiloHertz; and

a chopped voltage node operative to provide a chopped voltage V_CH having a substantially constant magnitude independent of the magnitude of the input voltage signal V_IN and substantially in the range from and including about 6 Volts to and including about 10 Volts,

wherein the pre-regulator circuit is operative to selectively generate the chopped voltage V_CH at the chopped voltage node in response to the PWM signal and the input voltage signal, and selectively operate in a sleep mode, whereby current through the pre-regulator circuit is restricted.

2. The low-frequency switching voltage pre-regulator circuit of claim 1 further comprising:

a chopping circuit coupled with the input node and being operative to receive the input voltage V_IN and generate a bucking signal at a buck node in response to a switching signal received via a current limiting resistor at a switching signal node;

a bucking circuit coupled with the chopping circuit at the buck node and being operative to generate the chopped voltage V_CH at the chopped voltage node in response to the bucking signal;

a feedback and sense circuit coupled with the chopped voltage node and being operative sense the magnitude of the chopped voltage V_CH and to provide a feedback signal at a feedback node in response to the magnitude of the chopped voltage V_CH; and

a pre-driver switching circuit coupled with the PWM input node and with the feedback node, the pre-driver circuit being operative to selectively generate the switching signal in response to the feedback signal and PWM signal.

3. The low-frequency switching voltage pre-regulator circuit of claim 2 wherein the chopping circuit comprises a low voltage, high speed three-terminal semiconductor switching device operative to propagate the input voltage V_IN to the buck node in response to the switching signal, and operative switch to a sleep mode.

4. The low-frequency switching voltage pre-regulator circuit of claim 3 wherein the a bucking circuit comprises:

a bucking coil coupled with the buck node and being operative to store electrical energy in response to the buck signal and to provide a bucking current at the chopped voltage node in response to the bucking signal; and

a charge well coupled with the chopped voltage node and being operative to provide the chopped voltage V_CH in response to the bucking current.

5. The low-frequency switching voltage pre-regulator circuit of claim 4 wherein the feedback and sense circuit comprises:

a sense diode coupled with the chopped voltage node and being operative to conduct current in response to the magnitude of the chopped voltage V_CH;

a resistor bias network coupled sense diode and being operative to provide a bias signal at a bias node; and

a low voltage, high speed three-terminal semiconductor switching device coupled with the bias node and being operative to generate the feedback signal in response to the bias signal.

6. The low-frequency switching voltage pre-regulator circuit of claim 5 wherein the pre-driver switching circuit comprises:

a resistor bias network coupled with the PWM input node and the feedback node and being operative to propagate the PWM signal in response to the feedback signal; and

a low voltage, high speed three-terminal semiconductor switching device coupled with the resistor bias network and the feedback node and being operative to generate the switching signal in response to the feedback signal and the PWM signal.

7. The low-frequency switching voltage pre-regulator circuit of claim 6 wherein switching device comprises an enhancement mode P-Channel MOSFET transistor having a drain-to-source withstand of at least 60 Volts.

8. The low-frequency switching voltage pre-regulator circuit of claim 6 wherein the switching device comprises a PNP bipolar transistor having a collector-emitter withstand of at least 60 Volts and having a two-terminal switchover bypass resistor having a first terminal coupled with a collector of the transistor and a second terminal coupled with an emitter of the transistor.

9. A voltage regulator circuit, comprising:

a switching pre-regulator circuit being operative to selectively generate a chopped voltage V_CH at a chopped voltage node in response to a low-frequency pulse width modulated (“

PWM”

) signal received at a PWM input node and an input voltage V_IN received at a voltage input node, where the input voltage V_IN is substantially in the range from about 20 Volts to about 58 Volts, and the chopped voltage V_CH has a substantially constant magnitude independent of the magnitude of the input voltage V_IN and substantially in the range from about 6 Volts to about 10 Volts; and

a linear voltage regulator circuit coupled with the chopped voltage node and being operative to generate a substantially regulated voltage at a voltage regulator output node in response to the chopped voltage V_CH.

10. The voltage regulator circuit according to claim 9, wherein the switching pre-regulator circuit comprises:

a feedback and sense circuit coupled with the chopped voltage node and being operative to generate a feedback signal at a feedback node in response to the chopped voltage V_CH;

a pre-driver switching circuit coupled with the feedback node and the PWM input node and being operative to generate a switching signal at a switching node in response to the PWM signal and the feedback signal; and

a chopping circuit having an input operative to receive the input voltage V_IN and an output defining the pre-regulator output, the chopping circuit being coupled with the switching node and being operative to generate the chopped voltage V_CH at the pre-regulator output node in response to the input voltage and being operative to restrict current to the output node in response to the switching signal.

11. The voltage regulator circuit according to claim 10, wherein the PWM signal comprises a modulated voltage signal having a duty cycle between approximately 25 percent and 50 percent, and a frequency between approximately 5 kiloHertz and 15 kiloHertz, the input voltage V_IN having a magnitude substantially in the range from and including about 20 Volts to and including about 58 Volts, and the chopped voltage V_CH having a magnitude substantially in the range from and including about 6 Volts to and including about 10 Volts.

12. The voltage regulator circuit according to claim 11, wherein the feedback and sense circuit comprises:

a sense diode coupled with the chopped voltage node and being operative to conduct current in response to the magnitude of the chopped voltage V_CH;

a resistor bias network coupled sense diode and being operative to provide a bias signal at a bias node; and

a low voltage, high speed three-terminal semiconductor switching device coupled with the bias node and being operative to generate the feedback signal in response to the bias signal.

13. The voltage regulator circuit according to claim 11, wherein the pre-driver switching circuit comprises:

a sense diode coupled with the chopped voltage node and being operative to conduct current in response to the magnitude of the chopped voltage V_CH;

a resistor bias network coupled sense diode and being operative to provide a bias signal at a bias node; and

a low voltage, high speed three-terminal semiconductor switching device coupled with the bias node and being operative to generate the feedback signal in response to the bias signal.

14. The voltage regulator circuit according to claim 13, wherein the chopping circuit comprises:

a power switch transistor operative to propagate the input voltage V_IN in response to the switching signal;

a bucking coil coupled with the power switch transistor and being operative to generate a bucking current at the chopped voltage node in response to the propagated input voltage V_IN;

a charge well coupled with the chopped voltage node and being operative to generate the chopping voltage at the chopped voltage node in response to the bucking current.

15. A cascade voltage regulator comprising:

a switching voltage pre-regulator means operative to receive an input voltage V_IN a low-frequency pulse width modulated (“

PWM”

) signal and for generating a chopped voltage V_CH at a chopped voltage node in response to a the PWM signal, where the input voltage V_IN is substantially in the range from about 20 Volts to about 58 Volts and the chopped voltage V_CH has a substantially constant magnitude independent of the magnitude of the input voltage V_IN and substantially in the range from about 6 Volts to about 10 Volts; and

a linear voltage regulating means coupled with the switching voltage pre-regulator means for receiving the chopped voltage output and for generating a regulated voltage output at a voltage regulator output node in response to the chopped voltage V_CH.

16. The voltage regulator according to claim 15, wherein the switching pre-regulator comprises:

a feedback means for generating a feedback signal responsive to the chopped voltage output;

a pre-driver switching means for receiving the feedback signal and the PWM signal and for generating a switching signal in response to the PWM signal and the feedback signal; and

a voltage chopping means for receiving the input voltage V_IN and the switching signal and for generating the chopped voltage in response to the switching signal.

17. The voltage regulator according to claim 16 wherein the PWM signal comprises a control signal generated by a microprocessor and having a frequency between about 5 kiloHertz and 15 kiloHertz and having about a 33 percent duty cycle, the input voltage V_IN comprises DC voltage having a magnitude substantially in the range from and including about 10 Volts to about and including 58 Volts, and the chopped voltage V_CH is approximately 7.6 Volts.

18. A method for controlling a voltage output in response to a input voltage, comprising:

selectively generating a chopped voltage signal in response to a pulse width modulated (“

PWM”

) signal received from microprocessor and an input voltage having a magnitude substantially within a range from and including about 20 Volts to and including about 58 Volts, the chopped voltage having a magnitude independent of the input voltage and being substantially within the range from and including about 6 Volts to and including about 10 Volts, the magnitude of the chopped voltage being independent of the magnitude of the input voltage.

19. The method of claim 18 further comprising the step of generating the PWM from a microprocessor circuit, the PWM signal having a frequency between about 5 kiloHertz and 15 kiloHertz and having about a 33 percent duty cycle.

20. The method of claim 19 further comprising generating a regulated voltage in response to the chopped voltage signal.