Method and circuit for reducing the power up time of a phase lock loop

• US 6,667,642 B1
• Filed: 09/18/2002
• Issued: 12/23/2003
• Est. Priority Date: 09/18/2002
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moyal, Nathan
• Primary Examiner(s): Wells, Kenneth B
• Application Number:
  US10/247,235
• Time in Patent Office: 461 Days
• Field of Search: 327/142, 327/143, 327/156-159, 331/DIG.2, 375/376
• US Class Current: 327/156
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A method and circuit for reducing the power up time of a phase lock loop (PLL). In one embodiment, the present invention cuts off a first voltage to the phase lock loop thereby powering down the phase lock loop. In power down, a second voltage is utilized to maintain the power requirements of the filter node within the phase lock loop while the other components of the phase lock loop are powered down. The PLL is now in a power down mode. The present invention then restores the first voltage to the PLL. Once the internal components of the PLL stabilize, the second voltage is disengaged from the filter node wherein the phase lock loop is powered up to operational power.

Claims

1. A phase lock loop (PLL) circuit comprising:

a plurality of PLL components each receiving power from a first power source for supplying power; and

a filter node of said PLL components, receiving power from a second power source for supplying power to said filter node, said second power source supplying power to said filter node during a power down period of said first power source.

2. The phase lock loop circuit of claim 1, wherein said second power source supplies power to said filter node at a reference voltage.

3. The phase lock loop circuit of claim 1 wherein during said power up period of said first power source, said filter node is cut off from said second power source and said filter node receives power from said first power source.

4. The phase lock loop circuit of claim 3 wherein during said power up period of said first power source said filter node is cut off from said second power source after a predetermined period of time has passed.

5. The phase lock loop circuit of claim 3 wherein during said power up period of said first power source said filter node is cut off from said second power source after said plurality of PLL components is biased up.

6. A method of reducing the power up time of a phase lock loop (PLL) circuit comprising:

cutting off a first voltage to components of said PLL, wherein the cutting off of said first voltage results in a powering down of said PLL;

utilizing a second voltage to maintain the power requirements of a filter node near operational mode within said PLL while said PLL is powered down; and

restoring said first voltage to said PLL to power up said PLL to operational power.

7. The method as recited in claim 6 further comprising:

programming a new frequency into said PLL.

8. The method as recited in claim 6 further comprising:

maintaining the same frequency of said PLL.

9. The method as recited in claim 8 further comprising:

sending a PLL start signal, said PLL start signal initiating a power up of at least one of the group consisting of a phase frequency detector (PFD) node, a pump node, and a voltage controlled oscillator (VCO) node within said components of said PLL.

10. The method as recited in claim 9 further comprising:

disengaging said second voltage from said filter node after said initiating of said power up of said PFD node, said pump node, said VCO node within said PLL, wherein said disengaging of said second voltage is based on a predetermined period of time.

11. The method as recited in claim 9 further comprising:

disengaging said second voltage from said filter node after said initiating of said power up of said PFD node, said pump node, said VCO node within said PLL, wherein said disengaging of said second voltage from said filter node is based on a power-up indicator.

12. The method as recited in claim 11 wherein after said component is biased up said power up indicator coupled with said component sends a signal to a decision gate.

13. The method as recited in claim 12 wherein said decision gate disengages said second voltage from said filter node after receiving said signal from said power up indicator.

14. The method as recited in claim 12 wherein said decision gate disengages said second voltage from said filter node after receiving said signal from each said power up indicator within said PLL.

15. A phase lock loop (PLL) circuit comprising:

a phase frequency detector (PFD) node for comparing a reference frequency with a feedback frequency;

a pump node for receiving a signal from said PFD node and establishing pump up and pump down signals based on said comparing;

a filter node for converting said pump up and pump down signals from said pump node to a voltage;

a voltage controlled oscillator (VCO) node for converting said voltage from said filter node into a frequency;

a divider node for receiving said frequency from said VCO node and dividing it down into said feedback frequency; and

a reference voltage for supplying power to said filter node during a portion of a PLL power down period.

16. The phase lock loop circuit of claim 15 wherein during said PLL power down at least one of the group consisting of said PFD node, said pump node, and said VCO node use no power.

17. The phase lock loop circuit of claim 15 wherein during a PLL power up period, said reference voltage is removed from said filter node.

18. The phase lock loop circuit of claim 17 wherein during said PLL power up period, said reference voltage is removed from said filter node after a predetermined period of time has passed.

19. The phase lock loop circuit of claim 17 wherein during said PLL power up period, said reference voltage is removed from said filter node after at least one of the group consisting of said PFD node, said pump node, and said VCO node is biased up to operational levels.

20. The phase lock loop circuit of claim 19 wherein a logic gate is utilized by said PLL in conjunction with a power up indicator (PUI) to establish when at least one of the group consisting of said PFD node, said pump node, and said VCO node are biased up to operational levels such that said reference voltage may be removed from said filter node.