Random number generator

• US 6,667,665 B2
• Filed: 07/29/2002
• Issued: 12/23/2003
• Est. Priority Date: 01/27/2000
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Janssen, Norbert
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US10/208,468
• Publication Number:
  US 20030006849A1
• Time in Patent Office: 512 Days
• Field of Search: 327/164, 331/78, 331/46, 331/47, 331/50, 708/250, 708/251, 714/739
• US Class Current: 331/78
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/40975 using encryption therefor
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator

Abstract

A random number generator on an integrated circuit has a first clock generator circuit with a first voltage supply for generating a first signal of a first frequency or of a first frequency range. A second clock generator circuit has a second voltage supply for generating a second signal of a second frequency or of a second frequency range, such that the second frequency or a mean value of the second frequency range is lower than the first frequency. A generator samples the first signal with the second signal and-generates at least one random number in dependence on the result of the sampling. The clock generator circuits are located as far away from one another as possible on the integrated circuit and/or the two voltage supplies are isolated from one another and/or at least one guard ring is placed around each of the clock generator circuits.

Claims

1. A circuit configuration, comprising:

an integrated circuit;

a random number generator configuration provided on said integrated circuit;

said random number generator configuration including a first clock generator circuit for generating a first signal having one of a first frequency and a first frequency range with a first mean value, and said random number generator configuration including a second clock generator circuit for generating a second signal having one of a second frequency and a second frequency range with a second mean value, said first and second clock generator circuits generating said first and second signals such that one of said second frequency and said second mean value is smaller than one of said first frequency and said first mean value;

said first clock generator circuit having a first voltage supply, said second clock generator circuit having a second voltage supply;

said random number generator configuration including a generator configured to sample said first signal with said second signal and configured to generate at least one random number in dependence of a sampling result; and

said first clock generator circuit and said second clock generator circuit being spaced apart from one another by a maximum spacing distance on said integrated circuit, and said first voltage supply and said second voltage supply being isolated from one another.

2. The circuit configuration according to claim 1, wherein:

said integrated circuit has diagonally opposite corner regions; and

said first and second clock generator circuits are respectively disposed in said diagonally opposite corner regions of said integrated circuit.

3. The circuit configuration according to claim 1, including at least one RC element, said first and second voltage supplies being isolated by said at least one RC element.

4. The circuit configuration according to claim 1, including two RC elements, each of said first and second voltage supplies being isolated by a respective one of said RC elements.

5. The circuit configuration according to claim 1, including an RC element for isolating said first clock generator circuit, said RC element having a decoupling frequency corresponding to one of said second frequency and said second mean value of said second frequency range of said second signal of said second clock generator circuit.

6. The circuit configuration according to claim 1, including an RC element for isolating said second clock generator circuit, said RC element having a decoupling frequency corresponding to one of said first frequency and said first mean value of said first frequency range of said first signal of said first clock generator circuit.

7. The circuit configuration according to claim 1, including at least one voltage regulator, said first and second voltage supplies being isolated by said at least one voltage regulator.

8. The circuit-configuration according to claim 1, wherein said first clock generator circuit generates a signal with a variable frequency as said first signal.

9. The circuit configuration according to claim 1, wherein said second clock generator circuit generates a signal with a variable frequency as said second signal.

10. The circuit configuration according to claim 1, wherein said first and second clock generator circuits generate said first and second signals such that said second signal has a frequency at least ten times lower than said first signal.

11. The circuit configuration according to claim 10, wherein said first and second clock generator circuits generate said first and second signals such that said second signal has a frequency at least one hundred times lower than said first signal.

12. The circuit configuration according to claim 1, wherein said generator generates a sequence of random numbers.

13. The circuit configuration according to claim 1, wherein said generator includes an equalizing circuit for compensating a non-constant power.

14. The circuit configuration according to claim 1, wherein said generator includes an equalizing circuit for providing a weighting during a random number generation.

15. The circuit configuration according to claim 1, wherein said generator includes an equalizing circuit with a linear feedback shift register.

19. The circuit configuration according to claim 1, including:

at least one guard ring placed around said first clock generator circuit; and

at least one guard ring placed around said second clock generator circuit.

16. A circuit configuration, comprising:

an integrated circuit;

a random number generator configuration provided on said integrated circuit;

said random number generator configuration including a first clock generator circuit for generating a first signal having one of a first frequency and a first frequency range with a first mean value, and said random number generator configuration including a second clock generator circuit for generating a second signal having one of a second frequency and a second frequency range with a second mean value, said first and second clock generator circuits generating said first and second signals such that one of said second frequency and said second mean value is smaller than one of said first frequency and said first mean value;

said first clock generator circuit having a first voltage supply, said second clock generator circuit having a second voltage supply;

said random number generator configuration including a generator configured to sample said first signal with said second signal and configured to generate at least one random number in dependence of a sampling result;

said random number generator configuration having at least one isolation measure selected from the group consisting of said first and second generator circuits being spaced apart from one another by a maximum spacing distance on said integrated circuit, said first and second voltage supplies being isolated from one another, and at least one guard ring being placed around each of said first and second clock generator circuits;

at least one of said first and second clock generator circuits having at least one voltage-coupled oscillator and a further oscillator; and

said at least one voltage-coupled oscillator having a control input, said further oscillator having a signal output connected to said control input of said at least one voltage-coupled oscillator.

17. The circuit configuration according to claim 16, wherein said further oscillator is a voltage-coupled oscillator having a control input supplied with a constant voltage.

18. The circuit configuration according to claim 16, wherein at least one of said first and second clock generator circuits has a plurality of voltage-coupled oscillators connected in series to one another such that each of said voltage-coupled oscillators, except for a last one of said voltage-coupled oscillators, has a control output connected to a control input of a respective next one of said voltage-coupled oscillators.