Flexible SONET access and transmission systems
First Claim
1. A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:
- a bus for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one LSU to each of the at least two LSUs; and
a backplane connected to the bus and having at least one bi-directional time slots for performing full time slot interchange between the at least two LSUs, wherein any of the at least two LSUs can read received data directly from one of the at least one bi-directional time slots and can place its transmit data into any other of the at least one bi-directional time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU, wherein the received and/or transmit data is transmitted between the LSUs via at least one segmented bus whereby said at least one segmented bus is connected to at least one HSU acting as a physical bridge between the segments, thereby allowing the LSUs on different segments to exchange data.
5 Assignments
0 Petitions
Accused Products
Abstract
A SONET network interface for interconnecting a high speed unit (HSU) with low speed interface units (LSUs) to enable transmission of signals therebetween. The interface including: a bus for interfacing the HSU with each of the LSU units to enable transmission of signals from each of LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs; and a backplane connected to the bus and having at least two time slots for performing full time slot interchange between the at least two LSUs, wherein any of the at least two LSUs can read received data directly from one of the at least two time slots and can place its transmit data into any other of the at least two time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU. In other embodiments, the HSU, LSUs, and bus are contained in a main shelf and mixing means are provided for allowing STM and ATM services to be mixed in the main shelf or an expansion shelf is provided containing expansion LSUs and an expansion interface unit (ESI) connected to the HSU of the main shelf for exchanging data between the main shelf and the expansion shelf; wherein STM services are performed in either the main shelf or the expansion shelf and ATM services are performed in the other of the main shelf or the expansion shelf.
-
Citations
30 Claims
-
1. A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:
-
a bus for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one LSU to each of the at least two LSUs; and
a backplane connected to the bus and having at least one bi-directional time slots for performing full time slot interchange between the at least two LSUs, wherein any of the at least two LSUs can read received data directly from one of the at least one bi-directional time slots and can place its transmit data into any other of the at least one bi-directional time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU, wherein the received and/or transmit data is transmitted between the LSUs via at least one segmented bus whereby said at least one segmented bus is connected to at least one HSU acting as a physical bridge between the segments, thereby allowing the LSUs on different segments to exchange data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
a first partition bus for interfacing the at least one HSU to a predetermined number of the at least two LSUs, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs; and
a second partition bus for interfacing the at least one HSU to a predetermined number of the at least two LSU units, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;
wherein the transmit data is transmitted between the LSUs via the first and second or third and forth buses through the at least one HSU acting as a physical bridge therebetween.
-
-
7. The SONET network interface of claim 1, wherein assignment of a time slot is performed on the backplane.
-
8. The SONET network interface of claim 1, wherein assignment of a time slot of a high speed signal is performed with an integrated circuit functioning as a switch matrix only when a bandwidth of said at least one HSU exceeds the bandwidth of said bus.
-
9. A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals therebetween, the method comprising the steps of:
-
interfacing the at least one HSU unit with each of the at least two LSU units via a bus to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs; and
performing full time slot interchange between the at least two LSUs via a backplane connected to the bus, the backplane having at least one bi-directional time slots, wherein any of the at least two LSUs can read received data directly from one of the at least one bi-directional time slots and can place its transmit data into any other of the at least one bi-directional time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU, wherein the received and/or transmit data is transmitted between the LSUs via at least one segmented bus whereby said at least one segmented bus is connected to at least one HSU acting as a physical bridge between the segments, thereby allowing the LSUs on different segments to exchange data. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
interfacing the at least one HSU to a predetermined number of the at least two LSUs via a first partition bus, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs; and
interfacing the at least one HSU to a predetermined number of the at least two LSU units via a second partition bus, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;
wherein the transmit data is transmitted between the LSUs via the first and second or third and forth buses through the at least one HSU acting as a physical bridge therebetween.
-
-
15. The method of claim 9, further comprising the step of performing assignment of a time slot on the backplane.
-
16. The method of claim 9, further comprising the step of performing assignment of a time slot of a high speed signal with an integrated circuit functioning as a switch matrix only when a bandwidth of said at least one HSU exceeds the bandwidth of said bus.
-
17. A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:
-
a bus for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSTJs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs, wherein the at least one ESU, at least two LSUs, and the bus are contained in a main shelf; and
mixing means for allowing STM and ATM services to be mixed in the main shelf, wherein the mixing means comprises a backplane connected to the bus and having at least one cell slot, the cell slot being mapped directly into a SONET SPE by the at least two LSU'"'"'s thereby avoiding the need for multiplexing on the at least one HSU, wherein any of the at least two LSUs can read received data directly from the at least one cell slot and can place its transmit data into the same or any other of the at least one cell slot, and wherein ATM cell arbitration for accessing the backplane cell slot to transmit ATM cells is implemented through arbitration lines used by ATM interface units to request a cell slot from a central arbitration unit. - View Dependent Claims (18, 19, 20, 21, 22, 23)
-
-
24. A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals therebetween, the method comprising the steps of:
-
interfacing the at least one HSU unit with each of the at least two LSU units via a bus to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs, wherein the at least one HSU, at least two LSUs, and the bus are contained in a main shelf; and
providing mixing means for allowing STM and ATM services to be mixed in the main shelf, wherein the providing step comprises the steps of;
connecting a backplane to the bus, the backplane having at least one cell slot, the cell slot being mapped directly into a SONET SPE by the at least two LSU'"'"'s thereby avoiding the need for multiplexing on the at least one HSU, wherein any of the at least two LSUs can read received data directly from the at least one cell slot and can place its transmit data into the same or any other of the at least one cell slot; and
accessing the backplane cell slot to transmit ATM cells for ATM cell arbitration through arbitration lines used by ATM interface units to request a cell slot from a central arbitration unit.- View Dependent Claims (25, 26, 27, 28, 29, 30)
-
Specification