Flexible SONET access and transmission systems

• US 6,667,973 B1
• Filed: 03/31/1999
• Issued: 12/23/2003
• Est. Priority Date: 04/29/1998
• Status: Expired due to Fees

• Current Assignee: Summit Technology Systems LP
• Original Assignee: Zhone Technologies Incorporated (DZS, Inc.)
• Inventors: Gorshe, Steven Scott, Brooks, Robert Wesley
• Primary Examiner(s): Yao, Kwang Bin
• Assistant Examiner(s): NGUYEN, HANH N
• Application Number:
  US09/282,405
• Time in Patent Office: 1,728 Days
• Field of Search: 370/907, 370/375, 370/376, 370/539, 370/357-360, 370/362-364, 370/377, 370/381, 370/384, 370/538, 370/541, 370/463, 370/401-403, 370/395, 370/438, 370/451, 370/502, 370/535, 370/419, 370/400, 370/372-374
• US Class Current: 370/376
• CPC Class Codes: H04J 2203/0026 Physical details
• CPC Class Codes: H04J 3/1611 Synchronous digital hierarchy [SDH] or SONET H04J3/1664 takes precedence for interactions with OTN
• CPC Class Codes: H04L 12/4035 in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit TDM/TDMA multiplex systems per se H04J3/1694; hybrid switching systems H04L12/64
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 49/405 Physical details, e.g. power supply, mechanical construction or backplane of ATM switches
• CPC Class Codes: H04L 49/606 Hybrid ATM switches, e.g. ATM&STM, ATM&Frame Relay or ATM&IP
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections
• CPC Class Codes: Y10S 370/907 Synchronous optical network, SONET

Abstract

A SONET network interface for interconnecting a high speed unit (HSU) with low speed interface units (LSUs) to enable transmission of signals therebetween. The interface including: a bus for interfacing the HSU with each of the LSU units to enable transmission of signals from each of LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs; and a backplane connected to the bus and having at least two time slots for performing full time slot interchange between the at least two LSUs, wherein any of the at least two LSUs can read received data directly from one of the at least two time slots and can place its transmit data into any other of the at least two time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU. In other embodiments, the HSU, LSUs, and bus are contained in a main shelf and mixing means are provided for allowing STM and ATM services to be mixed in the main shelf or an expansion shelf is provided containing expansion LSUs and an expansion interface unit (ESI) connected to the HSU of the main shelf for exchanging data between the main shelf and the expansion shelf; wherein STM services are performed in either the main shelf or the expansion shelf and ATM services are performed in the other of the main shelf or the expansion shelf.

Claims

1. A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:

a bus for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one LSU to each of the at least two LSUs; and

a backplane connected to the bus and having at least one bi-directional time slots for performing full time slot interchange between the at least two LSUs, wherein any of the at least two LSUs can read received data directly from one of the at least one bi-directional time slots and can place its transmit data into any other of the at least one bi-directional time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU,

wherein the received and/or transmit data is transmitted between the LSUs via at least one segmented bus whereby said at least one segmented bus is connected to at least one HSU acting as a physical bridge between the segments, thereby allowing the LSUs on different segments to exchange data.

2. The SONET network interface of claim 1, wherein some of the at least one bi-directional time slots comprise unused time slots and the at least two LSUs communicate with each other through the unused time slots.

3. The SONET network interface of claim 2, wherein a time slot used for performing full time slot interchange between the at least two LSUs is moved to another time slot if the time slot used for performing full time slot interchange between the at least two LSUs is needed for a connection between the at least one HSU and another of the at least two LSUs.

4. The SONET network interface of claim 3, wherein a LSU is moved to another time slot by provisioning the LSUs between which the full time slot interchange is performed to place their data onto the bus in the time slot they are currently using and the time slot to which they will move, taking data from the bus to the LSUs in the new time slot in which the LSU makes the move to the new time slot during an unused overhead time slot preventing data corruption during the move, and provisioning the LSUs to only place their data onto the bus in the new time slot.

5. The SONET network interface of claim 1, wherein the LSU which places its transmit data onto the bus for a full time slot interchange connection also drives a byte status signal for eliminating the need for individual asynchronous tributaries to perform VT or STS-1 pointer processing to locate a V5 or J1 byte.

6. The SONET network interface of claim 1, wherein the bus is a common bus and the SONET interface further comprises:

a first partition bus for interfacing the at least one HSU to a predetermined number of the at least two LSUs, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs; and

a second partition bus for interfacing the at least one HSU to a predetermined number of the at least two LSU units, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;

wherein the transmit data is transmitted between the LSUs via the first and second or third and forth buses through the at least one HSU acting as a physical bridge therebetween.

7. The SONET network interface of claim 1, wherein assignment of a time slot is performed on the backplane.

8. The SONET network interface of claim 1, wherein assignment of a time slot of a high speed signal is performed with an integrated circuit functioning as a switch matrix only when a bandwidth of said at least one HSU exceeds the bandwidth of said bus.

9. A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals therebetween, the method comprising the steps of:

interfacing the at least one HSU unit with each of the at least two LSU units via a bus to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs; and

performing full time slot interchange between the at least two LSUs via a backplane connected to the bus, the backplane having at least one bi-directional time slots, wherein any of the at least two LSUs can read received data directly from one of the at least one bi-directional time slots and can place its transmit data into any other of the at least one bi-directional time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU,

wherein the received and/or transmit data is transmitted between the LSUs via at least one segmented bus whereby said at least one segmented bus is connected to at least one HSU acting as a physical bridge between the segments, thereby allowing the LSUs on different segments to exchange data.

10. The method of claim 9, wherein some of the at least two time slots comprise unused time slots and the at least two LSUs communicate with each other through the unused time slots.

11. The method of claim 10, wherein a time slot used for performing full time slot interchange between the at least two LSUs is moved to another time slot if the time slot used for performing full time slot interchange between the at least two LSUs is needed for a connection between the at least one HSU and another of the at least two LSUs.

12. The method of claim 11, wherein the moving of the LSU to another time slot comprises:

provisioning the LSUs between which the full time slot interchange is performed to place their data onto the bus in the time slot they are currently using and the time slot to which they will move;

taking data from the bus to the LSUs in the new time slot in which the LSU makes the move to the new time slot during an unused overhead time slot preventing data corruption during the move; and

provisioning the LSUs to only place their data onto the bus in the new time slot.

13. The method of claim 9, wherein the LSU which places its transmit data onto the bus for a full time slot interchange connection also drives a byte status signal for eliminating the need for individual asynchronous tributaries to perform VT or STS-1 pointer processing to locate a V5 or J1 byte.

14. The method of claim 9, wherein the bus is a common bus and the method further comprises the steps of:

interfacing the at least one HSU to a predetermined number of the at least two LSUs via a first partition bus, the first partition bus being partitioned into a first bus for interfacing the at least one HSU to a first subset of the at least two LSUs and a second bus for interfacing the at least one HSU to a second subset of the at least two LSUs; and

interfacing the at least one HSU to a predetermined number of the at least two LSU units via a second partition bus, the second partition bus being partitioned into a third bus for interfacing the at least one HSU unit to the first subset of the at least two LSUs and a fourth bus for interfacing the at least one HSU unit with the second subset of the at least two LSUs;

wherein the transmit data is transmitted between the LSUs via the first and second or third and forth buses through the at least one HSU acting as a physical bridge therebetween.

15. The method of claim 9, further comprising the step of performing assignment of a time slot on the backplane.

16. The method of claim 9, further comprising the step of performing assignment of a time slot of a high speed signal with an integrated circuit functioning as a switch matrix only when a bandwidth of said at least one HSU exceeds the bandwidth of said bus.

17. A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween, the interface comprising:

a bus for interfacing the at least one HSU unit with each of the at least two LSU units to enable transmission of signals from each of the at least two LSTJs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs, wherein the at least one ESU, at least two LSUs, and the bus are contained in a main shelf; and

mixing means for allowing STM and ATM services to be mixed in the main shelf, wherein the mixing means comprises a backplane connected to the bus and having at least one cell slot, the cell slot being mapped directly into a SONET SPE by the at least two LSU'"'"'s thereby avoiding the need for multiplexing on the at least one HSU, wherein any of the at least two LSUs can read received data directly from the at least one cell slot and can place its transmit data into the same or any other of the at least one cell slot, and wherein ATM cell arbitration for accessing the backplane cell slot to transmit ATM cells is implemented through arbitration lines used by ATM interface units to request a cell slot from a central arbitration unit.

18. The SONET network interface of claim 17, wherein the bus is partitioned such that a portion of a STS-n signal is reserved for STM traffic on a first partition bus and the remaining STS-n signal is reserved for ATM traffic on a second partition bus.

19. The SONET network interface of claim 18, wherein the signal is an STS-3 signal and one STS-1 signal is used for STM traffic on the first partition bus and the remaining two STS-1 signals are used for ATM traffic on the second partition bus.

20. The SONET network interface of claim 17, wherein the central arbitration unit comprises the HSU which chooses which of the at least two LSUs transmits its cell into a next cell slot.

21. The SONET network interface of claim 20, wherein the HSU uses the last six clock periods of a cell slot to identify the LSU that is chosen to transmit its cell in the next cell slot.

22. The SONET network interface of claim 17, wherein cell multiplexing control is distributed such that when one of the at least two LSUs interfaces to, and receives cells over multiple facilities, that LSU is responsible to determine which cell to add to a backplane cell slot when that LSU makes cell arbitration requests to the central arbitration unit.

23. The SONET network interface of claim 17, wherein a same signal set is used for both ATM and STM multiplexing.

24. A method for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) in a SONET network interface to enable transmission of signals therebetween, the method comprising the steps of:

interfacing the at least one HSU unit with each of the at least two LSU units via a bus to enable transmission of signals from each of the at least two LSUs to the at least one HSU, and reception of the signals from the at least one HSU to each of the at least two LSUs, wherein the at least one HSU, at least two LSUs, and the bus are contained in a main shelf; and

providing mixing means for allowing STM and ATM services to be mixed in the main shelf, wherein the providing step comprises the steps of;

connecting a backplane to the bus, the backplane having at least one cell slot, the cell slot being mapped directly into a SONET SPE by the at least two LSU'"'"'s thereby avoiding the need for multiplexing on the at least one HSU, wherein any of the at least two LSUs can read received data directly from the at least one cell slot and can place its transmit data into the same or any other of the at least one cell slot; and

accessing the backplane cell slot to transmit ATM cells for ATM cell arbitration through arbitration lines used by ATM interface units to request a cell slot from a central arbitration unit.

25. The method of claim 24, further comprising the step of partitioning the bus such that a portion of a STS-n signal is reserved for STM traffic on a first partition bus and the remaining STS-n signal is reserved for ATM traffic on a second partition bus.

26. The method of claim 25, wherein the signal is an STS-3 signal and one STS-1 signal is used for STM traffic on the first partition bus and the remaining two STS-1 signals are used for ATM traffic on the second partition bus.

27. The method of claim 24, wherein the central arbitration unit comprises the HSU which chooses which of the at least two LSUs transmits its cell into a next cell slot.

28. The method of claim 27, further comprising the step of using the last six clock periods of a cell slot to identify the LSU that is chosen to transmit its cell in the next cell slot.

29. The method of claim 24, wherein the central arbitration unit comprises at least one of the LSU'"'"'s functioning as a common processing unit which chooses which of another of the at least two LSUs transmits its cell into a next cell slot.

30. The method of claim 24, further comprising distributing cell multiplexing control such that when one of the at least two LSUs interfaces to, and receives cells over multiple facilities, that LSU is responsible to determine which cell to add to a backplane cell slot when that LSU makes cell arbitration requests to the central arbitration unit.