Communication channel

• US 6,667,993 B1
• Filed: 08/03/1999
• Issued: 12/23/2003
• Est. Priority Date: 10/22/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lippett, Mark, Collivignarelli, Marco, Colquhoun, Steve
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): Tran, Thien D
• Application Number:
  US09/368,055
• Time in Patent Office: 1,603 Days
• Field of Search: 370/503, 370/505, 370/506, 370/507, 370/508, 370/509, 370/510, 370/512, 370/516, 370/513, 370/514, 370/519, 370/520, 375/260, 375/363, 375/364, 375/365, 375/366, 375/374
• US Class Current: 370/509
• CPC Class Codes: H04L 25/03866 using scrambling
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A digital system (100) has two or more nodes (120, 130) and a communication channel (110, 111) for transferring a single stream of ordered data from one node to another. The communication channel (110) has a number of data links (110a-110g) for transferring a plurality of sub-streams of data in a parallel fashion in order to transfer more data than a single data link is capable of transferring. Receivers (132a-132g) each have synchronizing circuitry (200, 202) for synchronizing a byte clock and a frame pulse of each received data sub-stream to the byte clock and frame pulse of a preselected master one of the receivers such that inherent data skew is eliminated.

Claims

1. A method for transferring a single stream of ordered data over a plurality of data links each having a transmitter and a receiver, wherein the single stream of data comprises a plurality of words each having a plurality of bits, comprising the steps of:

dividing the single stream of data into a plurality of sub-streams of data;

inserting a frame pulse periodically in each sub-stream of data;

transmitting each sub-stream of data over a corresponding data link of the plurality of data links in a parallel manner;

receiving each sub-stream of data to form a plurality of received data sub-streams, wherein a first data link has a first delay time that is different from a second delay time of a second data link, such that a data skew occurs between a first received data sub-stream and a second received data sub-stream;

recovering a byte clock from each received data sub-stream;

synchronizing the byte clock and frame pulse of each received data sub-stream to the byte clock and frame pulse of the first received data sub-stream such that the data skew is eliminated; and

combining the plurality of received data sub-streams to form a single received stream of ordered data; and

wherein the step of synchronizing comprises the steps of;

a) testing for frame synchronization by determining if the frame pulse of each of the received data sub-streams is synchronized with the frame pulse of the first received data sub-stream;

b) shifting a byte tap point in each of the received data sub-streams other than the first received data sub-stream up to a first number of times until each received data sub-stream is frame synchronized with the first received data sub-stream;

c) detecting a lack of frame synchronization when all received data sub-streams are not frame synchronized after the step of shifting a byte tap point a first number of times;

d) shifting a byte tap point in the first received data sub-stream by one position after the step of detecting a lack of frame synchronization; and

e) then repeating step b until each received data sub-stream is frame synchronized with the first received data sub-stream.

3. The method according to claim 1, wherein the step of synchronizing further comprises the steps of:

forcing the byte clock of each data link to align approximately with the byte clock of the first data link; and

shifting a bit tap point on each received data sub-stream so that byte boundaries of each received data sub-stream align with the byte clock associated with each received data sub-stream.

4. The method according to claim 1, further comprising the step of repeating the steps c, d, and e up to a second number of times until each received data sub-stream is frame synchronized with the first received data sub-stream.

2. A method for receiving a single stream of ordered data over a plurality of data links each having a transmitter and a receiver, wherein the single stream of data comprises a plurality of words each having a plurality of bits, and wherein the single stream of data is divided in a plurality of sub-streams of data with a frame pulse inserted periodically in each sub-stream of data, comprising the steps of:

receiving each sub-stream of data over a corresponding data link of the plurality of data links in a parallel manner to form a plurality of received data sub-streams, wherein a first data link has a first delay time that is different from a second delay time of a second data link, such that a data skew occurs between a first received data sub-stream and a second received data sub-stream;

recovering a byte clock from each received data sub-stream;

synchronizing the byte clock and frame pulse of each received data sub-stream to the byte clock and frame pulse of the first received data sub-stream such that the data skew is eliminated; and

combining the plurality of received data sub-streams to form a single received stream of ordered data; and

wherein the step of synchronizing comprises the steps of;

a) testing for frame synchronization by determining if the frame pulse of each of the received data sub-streams is synchronized with the frame pulse of the first received data sub-stream;

b) shifting a byte tap point in each of the received data sub-streams other than the first received data sub-stream up to a first number of times until each received data sub-stream is frame synchronized with the first received data sub-stream;

c) detecting a lack of frame synchronization when all received data sub-streams are not frame synchronized after the step of shifting a byte tap point a first number of times;

d) shifting a byte tap point in the first received data sub-stream by one position after the step of detecting a lack of frame synchronization; and

e) then repeating step b until each received data sub-stream is frame synchronized with the first received data sub-stream.

5. The method according to claim 2, wherein the step of synchronizing further comprises the steps of:

forcing the byte clock of each data link to align approximately with the byte clock of the first data link; and

shifting a bit tap point on each received data sub-stream so that byte boundaries of each received data sub-stream align with the byte clock associated with each received data sub-stream.

6. The method according to claim 2, further comprising the step of repeating the steps c, d, and e up to a second number of times until each received data sub-stream is frame synchronized with the first received data sub-stream.

7. A digital system having a first node and a second node and a communication channel connected between operable to transfer a single stream of ordered data over the communication channel, wherein the single stream of data comprises a plurality of words each having a plurality of bits, wherein the communication channel further comprises:

circuitry for dividing the single stream of ordered data into a plurality of sub-streams of data;

a plurality of data links each having a transmitter and a receiver, the plurality of data links operable to transmit each sub-stream of data over a corresponding data link of the plurality of data links in a parallel manner to form a plurality of received data sub-streams, wherein a first data link has a first delay time that is different from a second delay time of a second data link, such that a data skew occurs between a first received data sub-stream and a second received data sub-stream;

circuitry for inserting a frame pulse periodically in each sub-stream of data connected to each transmitter;

circuitry for combining the plurality of received data sub-streams connected to each receiver to form a single received stream of ordered data;

wherein each receiver further comprises;

circuitry for recovering a byte clock from the received data sub-stream; and

circuitry for synchronizing the byte clock and frame pulse of each received data sub-stream to the byte clock and frame pulse of a preselected master one of the receivers such that the data skew is eliminated;

wherein the circuitry for synchronizing is operable to perform the steps of;

a) testing for frame synchronization by determining if the frame pulse of each of the received data sub-streams is synchronized with the frame pulse of the first received data sub-stream;

b) shifting a byte tap point in each of the received data sub-streams other than the first received data sub-stream up to a first number of times until each received data sub-stream is frame synchronized with the first received data sub-stream;

c) detecting a lack of frame synchronization when all received data sub-streams are not frame synchronized after the step of shifting a byte tap point a first number of times;

d) shifting a byte tap point in the first received data sub-stream by one position after the step of detecting a lack of frame synchronization; and

e) then repeating step b until each received data sub-stream is frame synchronized with the first received data sub-stream.

8. The digital system according to claim 7, wherein the circuitry for synchronizing comprises:

circuitry for forcing the byte clock of the receiver to align approximately with the byte clock of the master receiver; and

bit shifter circuitry with a bit tap point operable to align byte boundaries of the received data sub-stream with the byte clock of the receiver.

9. The digital system according to claim 8, wherein the synchronizing circuitry further comprises:

frame check circuitry operable to test for frame synchronization by determining if the frame pulse of the received data sub-stream is synchronized with the frame pulse of the master receiver; and

a byte pipe with a byte tap point operable to delay the received data sub-stream a first number of bytes in response to the frame check circuitry so that the received data sub-stream is frame synchronized with the received data sub-stream of the master receiver.

10. A digital system having a communication channel, the digital system being operable to receive a single stream of ordered data over the communication channel, wherein the single stream of data comprises a plurality of words each having a plurality of bits, wherein the communication channel further comprises a plurality of receivers, each receiver operable to receive a data sub-stream, each receiver comprising:

circuitry for recovering a byte clock from the received data sub-stream; and

circuitry for synchronizing the byte clock and frame pulse of each received data sub-stream to the byte clock and frame pulse of a preselected master one of the receivers such that the data skew is eliminated, the circuitry for synchronizing comprising;

circuitry for forcing the byte clock of the receiver to align approximately with the byte clock of the master receiver; and

bit shifter circuitry with a bit tap point operable to align byte boundaries of the received data sub-stream with the byte clock of the receiver; and

wherein the circuitry for synchronizing is operable to perform the steps of;

a) testing for frame synchronization by determining if the frame pulse of each of the received data sub-streams is synchronized with the frame pulse of the first received data sub-stream;

b) shifting a byte tap point in each of the received data sub-streams other than the first received data sub-stream up to a first number of times until each received data sub-stream is frame synchronized with the first received data sub-stream;

c) detecting a lack of frame synchronization when all received data sub-streams are not frame synchronized after the step of shifting a byte tap point a first number of times;

d) shifting a byte tap point in the first received data sub-stream by one position after the step of detecting a lack of frame synchronization; and

e) then repeating step b until each received data sub-stream is frame synchronized with the first received data sub-stream.

11. The digital system according to claim 10, wherein the synchronizing circuitry further comprises:

frame check circuitry operable to test for frame synchronization by determining if the frame pulse of the received data sub-stream is synchronized with the frame pulse of the master receiver; and

a byte pipe with a byte tap point operable to delay the received data sub-stream a first number of bytes in response to the frame check circuitry so that the received data sub-stream is frame synchronized with the received data sub-stream of the master receiver.