System and method for initiating a serial data transfer between two clock domains

• US 6,668,292 B2
• Filed: 03/11/2002
• Issued: 12/23/2003
• Est. Priority Date: 08/31/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Meyer, Derrick R., Madrid, Philip Enrique
• Primary Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US10/095,019
• Publication Number:
  US 20020090046A1
• Time in Patent Office: 652 Days
• Field of Search: 710/61, 710/58, 710/305, 710/400, 235/380, 375/354
• US Class Current: 710/61
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received. The remainder of the serial data stream is received at appropriate intervals of the second clock rate.

Claims

1. A method for initiating a serial data stream between a transmitter and a receiver, wherein the transmitter operates according to at least a first clock having a first clock rate, wherein the receiver operates according to at least a second clock having a second clock rate, wherein a ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one, the method comprising:

providing a first state over a serial line between the transmitter and the receiver;

providing one or more start bits over said serial line, wherein said one or more start bits indicate a second state different from said first state;

providing one or more ratio bits over said serial line after said start bit, wherein said one or more ratio bits indicate said ratio between the second clock rate and the first clock rate;

receiving said one or more start bits;

using a transition between said first state and said second state to receive said one or more ratio bits; and

receiving a remainder of said serial data stream at intervals of said second clock rate.

2. The method of claim 1, wherein said receiving said one or more start bits occurs on an edge of said second clock, and wherein said using a transition between said first state and said second state to receive said one or more ratio bits occurs on an edge of said second clock.

3. The method of claim 2, wherein said receiver is further configured to operate according to a slow clock having a slow clock rate, wherein the ratio of the second clock rate to the slow clock rate is a second integer number greater than 1, the method further comprising:

receiving said one or more start bits on an edge of said slow clock prior to said receiving said one or more start bits on said edge of said second clock; and

receiving said one or more ratio bits on an edge of said slow clock prior to said using a transition between said first state and said second state to receive said one or more ratio bits on said edge of said second clock.

4. The method as recited in claim 3 further comprising decoding said ratio bit to determine said first clock rate.

5. The method as recited in claim 1, wherein said intervals of said second clock rate correspond to said first clock rate.

6. A computer system, comprising:

a memory configured to store initialization information for said computer system, wherein said initialization information begins with a start bit and a ratio bit, wherein said ratio bit is encoded with a ratio between a second clock rate and a first clock rate;

logic coupled to said memory for transmitting said initialization information, wherein said logic is configured to operate according to said first clock rate, and wherein said logic is configured to transmit said initialization information at said first clock rate; and

at least one processor coupled to receive a first system clock operating at said first clock rate and a second system clock operating at said second clock rate, wherein said at least one processor is configured to operate according to said second system clock, wherein said ratio is an integer number greater than or equal to one, wherein said at least one processor is further coupled to said logic with a serial line over which to receive said initialization information;

wherein said logic is configured transmit said initialization information over said serial line to said at least one processor, wherein said logic is further configured to transmit a first state over said serial line prior to said start bit, wherein said start bit includes a second state different from said first state; and

wherein said at least one processor is further configured to receive said start bit and to use a transition between said first state and said second state to receive said ratio bit, and wherein said processor is further configured to decode said ratio bit to determine said first clock rate to receive a remainder of said initialization information.

7. The system of claim 6, wherein said at least one processor is further configured to operate at a fast clock rate, wherein the ratio between said fast clock rate and said second clock rate is an integer greater than or equal to one.

8. The computer system of claim 6 further comprising a bridge that includes said memory and said logic.

9. The computer system as recited in claim 6, wherein said at least one processor is further configured to store said one or more ratio bits within a register.

10. The computer system as recited in claim 6, wherein said at least one processor is further configured to receive said one or more ratio bits on an edge of said second clock.