Scalable architecture based on single-chip multiprocessing

• US 6,668,308 B2
• Filed: 06/08/2001
• Issued: 12/23/2003
• Est. Priority Date: 06/10/2000
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Barroso, Luiz Andre, Nowatzyk, Andreas, Gharachorloo, Kourosh
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): LI, ZHUO H
• Application Number:
  US09/877,793
• Publication Number:
  US 20020046324A1
• Time in Patent Office: 928 Days
• Field of Search: 711/118, 711/119, 711/141, 711/145, 711/127, 711/128, 711/147.5, 711/203.205, 711/5, 711/105, 711/149, 711/157, 711/209, 711/122, 370/295.31, 370/395.5, 370/351, 370/356, 709/213, 365/189.04, 365/220, 365/230.03, 365/230.04, 365/230.05
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0826 Limited pointers directories; State-only directories without pointers
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads. A showcase example of the chip-multiprocessing system, called the PIRANHA™ system, is a highly integrated processing node with eight simpler ALPHA™ processor cores. A method for scalable chip-multiprocessing is also provided.

Claims

1. A chip-multiprocessing system with scalable architecture, comprising, on a single chip:

a plurality of processor cores;

a two-level cache hierarchy including;

a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches; and

a second level cache with a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules, each of the plurality of interleaved modules having its own controller, on-chip tag and data storage;

one or more memory controllers capable of operatively communicating with the two-level cache hierarchy and with an off-chip memory, each of the plurality of interleaved modules being attached to one of the memory controllers which interfaces to a bank of memory chips;

a cache coherence protocol;

one or more coherence protocol engines;

an intra-chip switch; and

an interconnect subsystem.

2. A chip-multiprocessing system as in claim 1, wherein the controllers in the plurality of interleaved modules are responsible for enforcing coherence within the single chip.

3. A chip-multiprocessing system as in claim 1, wherein access to a specific one of the one or more memory controllers is controlled by and muted through a corresponding one of controllers in the plurality of interleaved modules.

4. A chip-multiprocessing system with scalable architecture, comprising on a single chip:

a plurality of processor cores;

a two-level cache hierarchy including;

a pair of instruction and data caches for, and private to, each processor core, the pair being first level caches; and

a second level cache with a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores, the second level cache being modular with a plurality of interleaved modules, each of the plurality of interleaved modules having its own control logic for maintaining intra-chip coherence and cooperation with the plurality of coherence protocol engines and an intra-chip switch interface for intra-chip communication within the single chip;

one or more memory controllers capable of operatively communicating with the two-level cache hierarchy and with an off-chip memory, each of the plurality of interleaved modules having a dedicated interface to one of the one or more memory controllers;

a cache coherence protocol;

one or more coherence protocol engines;

an intra-chip switch; and

an interconnect subsystem.