Automatic integrated circuit design kit qualification service provided through the internet

• US 6,668,360 B1
• Filed: 01/08/2001
• Issued: 12/23/2003
• Est. Priority Date: 01/08/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Louis
• Primary Examiner(s): Garbowski, Leigh M.
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US09/755,569
• Time in Patent Office: 1,079 Days
• Field of Search: 716/4, 716/1
• US Class Current: 716/106
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A circuit qualification system is constructed to allow multiple vendors or circuit designers to automatically qualify their integrated circuit designs for use on the same die providing a single integrated circuit design which is qualified to work under pre-specified conditions. This qualification system contains knowledge of design rules, design automation tools, design automation licenses, and a qualification flow which is the path the automatic qualification system follows based on user input selections. The qualification or common verification system, which is available via the Internet or some other communication network, provides circuit designers with an interface where circuit designs can be submitted for automatic qualification. This interface informs the circuit designers how to submit the required data and to setup the qualification options. The interface also provides an output to the circuit designers telling them if their circuit design is error-free and if it passes verification and qualification and licensing for the overall integrated circuit design.

Claims

1. A method for verifying designs of a plurality of integrated circuits created by one or more design groups comprising the steps of:

obtaining multiple designs, technology rules, and specifications from multiple locations,

creating a technology definition database detailing physical semiconductor parameters for electronic devices that form said integrated circuits;

creating a simulation model database detailing electronic component models of the electronic devices;

creating a design rule database detailing the physical dimension constraints of said integrated circuits;

transferring the technology database, the simulation model database, and the design rule database to a central data repository;

granting a license to access to the central data repository to use the technology database, the simulation model database, and the design rule database;

generating a quality assurance process to verify function and structure of the integrated circuits;

installing said quality assurance process on said central data repository;

granting a license to said design groups to have access to said central data repository to use said quality assurance process to verify function and structure of said integrated circuits;

submitting the integrated circuit designs for verification of function and structure by said quality assurance process;

retrieving results of said quality assurance process;

correcting any errors found by said quality assurance process in the integrated circuits; and

repeating the steps of submitting, retrieving, and correcting until the integrated circuit contains no errors.

2. The method of claim 1 wherein the central data repository is a node of a global computing network, whereby the technology database, the simulation model database, the design rule database, and the quality assurance process are accessed by the design groups through said global computing network.

3. The method of claim 1 where in the quality assurance flow comprises the steps of:

creating a simulation model for testing the logic and circuit function using the specified requirements;

creating simulation test patterns which represent the required specified function;

performing a unit delay simulation to test the logic design with binary logic levels;

checking if simulation agrees with an original specification of said integrated circuit design;

issuing a user report if simulation fails in order to inform the design group of said integrated circuits which mistakes were found and to suggest corrections for the errors;

placing &

routing physical circuits according the semiconductor process ground rules in order to prepare for fabrication of the integrated circuits;

physically merging multiple macros to combine multiple designs from at least one of the design groups;

checking design rules of the combined multiple designs to insure the combined design obeys the process ground rules;

issuing a user report if checking of the design rules fails to inform the designer of the mistakes found;

suggesting corrections to errors found with the checking of the design;

simulating and analyzing timing of the combined multiple designs with layout delays included to test the binary logic levels in the presence of circuit delays;

verifying exhaustively a final layout of the combined multiple designs to guarantee the semiconductor ground rules are obeyed;

issuing a user report if simulating of timing and verifying of layout is not successful;

preparing chip test patterns based on simulation patterns to insure the combined multiple designs;

to verifying functioning of semiconductor substrates containing combined multiple designs;

issuing final user report to inform the design group that the combined multiple designs have successfully passed the automatic qualification flow and that the combined multiple design is ready for fabrication.

4. The method of claim 3 further comprising the step of:

combining a group of said combined multiple designs from different design groups on a semiconductor substrate.

5. An apparatus for verifying a design of a plurality of integrated circuits created by one or more design groups comprising:

means for obtaining multiple designs, technology rules, and specifications from multiple locations,

means for creating a technology definition database detailing physical semiconductor parameters for electronic devices that form said integrated circuits;

means for creating a simulation model database detailing electronic component models of the electronic devices;

means for creating a design rule database detailing the physical dimension constraints of said integrated circuits;

means for transferring the technology database, the simulation model database, and the design rule database to a central data repository;

means for granting a license to access to the central data repository to use the technology database, the simulation model database, and the design rule database;

means for generating a quality assurance process to verify function and structure of the integrated circuits;

means for installing said quality assurance process on said central data repository;

means for granting a license to said design groups to have access to said central data repository to use said quality assurance process to verify function and structure of said integrated circuits;

means for submitting the integrated circuit designs for verification of function and structure by said quality assurance process;

means for retrieving results of said quality assurance process;

means for correcting any errors found by said quality assurance process in the integrated circuits; and

means for repeating the steps of submitting, retrieving, and correcting until the integrated circuit contains no errors.

6. The apparatus of claim 5 wherein the central data repository is a node of a global computing network, whereby the technology database, the simulation model database, the design rule database, and the quality assurance process are accessed by the design groups through said global computing network.

7. The apparatus of claim 5 where in the quality assurance flow comprises the steps of:

means for creating a simulation model for testing the logic and circuit function using the specified requirements;

means for creating simulation test patterns which represent the required specified function;

means for performing a unit delay simulation to test the logic design with binary logic levels;

means for checking if simulation agrees with an original specification of said integrated circuit design;

means for issuing a user report if simulation fails in order to inform the design group of said integrated circuits which mistakes were found and to suggest corrections for the errors;

means for placing &

routing physical circuits according the semiconductor process ground rules in order to prepare for fabrication of the integrated circuits;

means for physically merging multiple macros to combine multiple designs from at least one of the design groups;

checking design rules of the combined multiple designs to insure the combined design obeys the process ground rules;

means for issuing a user report if checking of the design rules fails to inform the designer of the mistakes found;

suggesting corrections to errors found with the checking of the design;

means for simulating and analyzing timing of the combined multiple designs with layout delays included to test the binary logic levels in the presence of circuit delays;

means for verifying exhaustively a final layout of the combined multiple designs to guarantee the semiconductor ground rules are obeyed;

means for issuing a user report if simulating of timing and verifying of layout is not successful;

means for preparing chip test patterns based on simulation patterns to insure the combined multiple designs;

to verifying functioning of semiconductor substrates containing combined multiple designs;

means for issuing final user report to inform the design group that the combined multiple designs have successfully passed the automatic qualification flow and that the combined multiple design is ready for fabrication.

8. The apparatus of claim 7 further comprising:

means for combining a group of said combined multiple designs from different design groups on a semiconductor substrate.

9. A system for automatically verifying design of a plurality of integrated circuits created by one or more design organizations, comprising:

An interface for obtaining multiple designs, technology rules, and specifications from multiple locations,

A technology definition database containing a description of a semiconductor fabrication process to be used to construct said plurality of integrated circuits;

A simulation model database containing circuit and device models detailing functional operation of circuits and devices incorporated in said plurality integrated circuits;

A design rule database containing a description of physical constraints of electronic devices, geometric constraint of interconnect wiring; and

physical separations of the electronic devices and the interconnect wiring;

An integrated circuit database containing a description of the plurality of integrated circuits;

A plurality of design automation apparatus in communication with the technology definition database, the simulation model database, the design rule database and the integrated circuit database for verifying the design of the plurality of integrated circuits; and

a verification apparatus coupled to the plurality of design automation apparatus to monitor the operation of the plurality of design automation apparatus, to generate design verification reports indicating correctness of the plurality of said integrated circuits, and to communicate said reports to said design organization.

10. The system of claim 9 further comprising a licensing apparatus to communicate with the verification apparatus to grant permission to the design organization for use of said system.

11. The system of claim 9 further comprising a communication interface in communication with a digital communication network to allow the plurality design organizations to communicate with said system in communication with the integrated circuit database to allow transfer of the description of the plurality of integrated circuits from the design organization to the integrated circuit database, and in communication with the verification apparatus to receive the design verification reports.

12. The system of claim 10 further comprising claim 11 which is in communication with the licensing apparatus through the verification apparatus to communicate requests for permission granting or denying said permission.

13. The system of claim 10 where in the verification apparatus comprises:

a simulation model generator in communication with the simulation model database and the integrated circuit database to create simulation models of the plurality of integrated circuits;

a test pattern generator in communication with the integrated circuits database to define the stimulus to and response from the plurality of integrated circuits;

a unit delay simulator to the simulation model generator and the test pattern generator to simulate the plurality of integrated circuits to verify basic function of said plurality of integrated circuits not including timing delay parameters of the plurality of integrated circuits;

a design rule checking apparatus in communication with the integrated circuits database and the design rule database to compare physical design of the plurality of integrated circuits to the design rule;

a total circuit simulator in communication with the simulation model generator and the test pattern generator to simulate a combination of the plurality of integrated circuit merged for placement on a semiconductor substrate;

a timing analyzer in communication with the simulation model generator and the test pattern generator to analyze timing delays of the merged plurality of integrated circuits;

a physical layout verification apparatus in communication with the design rule database and the integrated circuit design database to verify the placement of components and interconnections of the plurality of integrated circuits merged on the semiconductor substrate;

and a reporting apparatus in communication with the plurality of design organizations to report results of the design rule checking apparatus, the total circuit simulator, the timing analyzer, and the physical layout verification apparatus.

14. A program retention device containing program instruction code executable on at least one networked computing device for verifying a design of a plurality of integrated circuits created by one or more design groups, whereby said program performs the steps of:

obtaining multiple designs, technology rules, and specifications from multiple locations,

creating a technology definition database detailing physical semiconductor parameters for electronic devices that form said integrated circuits;

creating a simulation model database detailing electronic component models of the electronic devices;

creating a design rule database detailing the physical dimension constraints of said integrated circuits;

transferring the technology database, the simulation model database, and the design rule database to a central data repository;

granting a license to access to the central data repository to use the technology database, the simulation model database, and the design rule database;

generating a quality assurance process to verify function and structure of the integrated circuits;

installing said quality assurance process on said central data repository;

granting a license to said design groups to have access to said central data repository to use said quality assurance process to verify function and structure of said integrated circuits;

submitting the integrated circuit designs for verification of function and structure by said quality assurance process;

retrieving results of said quality assurance process;

correcting any errors found by said quality assurance process in the integrated circuits; and

repeating the steps of submitting, retrieving, and correcting until the integrated circuit contains no errors.