Device transfer method

• US 6,669,801 B2
• Filed: 05/09/2001
• Issued: 12/30/2003
• Est. Priority Date: 01/21/2000
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshimura, Tetsuzo, Wang, Wen-chou Vincent, McCormack, Mark Thomas, Roman, James, Inao, Masaaki
• Primary Examiner(s): MAYES, MELVIN C
• Application Number:
  US09/853,353
• Publication Number:
  US 20020036055A1
• Time in Patent Office: 965 Days
• Field of Search: 156/230, 156/235, 156/289, 156/297, 156/234
• US Class Current: 156/230
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/82005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01105 : Rare earth metals
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: Y10T 156/1089 : of discrete laminae to single face of additional lamina

Abstract

A method for transferring devices to a device substrate is disclosed. In one embodiment, the method includes providing an array of devices on a carrier substrate having a generally horizontal surface, where the array comprises multiple device pluralities. The method includes tilting the device pluralities with respect to the generally horizontal surface of the carrier substrate. Each tilted device plurality is preferably in substantially the same pattern, and each tilted device plurality is placed on device regions on respective device substrates.

Claims

1. A method for transferring a device from one substrate to another substrate comprising:

coupling a device to a generally horizontal surface of a first substrate;

tilting the device with respect to the generally horizontal surface of the first substrate; and

transferring the tilted device from the first substrate to a second substrate,

wherein said coupling comprises disposing a release layer on the generally horizontal surface of the first substrate;

disposing at least one tilting layer on the release layer; and

placing said device on the tilting layer.

2. The method of claim 1 wherein said tilting the device comprises releasing at least a portion of the release layer from the horizontal surface of the first substrate.

3. The method of claim 1 additionally comprising disposing a second type device on the tilting layer.

4. A method for transferring a device from one substrate to another substrate comprising:

coupling a device to a generally horizontal surface of a first substrate;

titling the device with respect to the generally horizontal surface of the first substrate; and

transferring the tilted device from the first substrate to a second substrate,

wherein said tilting is by a magnetic field application.

5. A method comprising:

forming a first and second plurality of devices on a formation substrate;

transferring the first plurality and the second plurality of devices to a carrier substrate;

tilting the first plurality and the second plurality of devices with respect to a horizontal surface of the carrier substrate;

placing the first plurality of devices on a first plurality of device regions on a first device substrate; and

placing the second plurality of devices on a second plurality of device regions on a second device substrate.

6. The method of claim 5 further comprising:

bonding the first plurality of devices to the first plurality of device regions; and

bonding the second plurality of devices to the second plurality of device regions.

7. The method of claim 5 further comprising:

bonding the first plurality of devices to the first plurality of device regions using a bonding material disposed on the first plurality of device regions; and

bonding the second plurality of devices to the second plurality of device regions using a bonding material disposed on the second plurality of device regions.

8. The method of claim 5 further comprising, after forming the first and second plurality of devices on the formation substrate:

forming trenches to separate each of the devices in the first and second plurality from each other.

9. The method of claim 5 where the first and second pluralities of devices have the same pattern.

10. The method of claim 5 wherein the first and second pluralities of devices have the same pattern, and wherein at least one device in the first device plurality on the carrier substrate is disposed between at least two adjacent devices in the second device plurality.

11. The method of claim 5 further comprising, prior to transferring:

separating the first and second plurality of devices from the formation substrate using a lift-off process.

12. The method of claim 5 further comprising, prior to transferring:

separating the first and second plurality of devices from the formation substrate using an epitaxial lift-off process.

13. The method of claim 5 wherein forming the first and second pluralities of devices on the formation substrate comprises forming the first and second pluralities of devices on a release layer on the formation substrate.

14. The method of claim 5 wherein the first plurality of devices comprises at least one of a wavelength filter, a mirror, a hologram, a grating, a light-emitting film, a photodiode, a VCSEL, optical switch, photonic crystal, LD, photo detector, transceiver chip, IC, LSI, light modulator, tunable filter, wavelength switch and a thin film structure.

15. The method of claim 5 further comprising:

forming a capacitor embedded film using the first plurality of devices on the first device substrate.

16. The method of claim 5 wherein the carrier substrate is a first carrier substrate, and wherein the method further comprises:

providing a third plurality of devices and a fourth plurality of devices on a second carrier substrate;

tilting the third plurality and fourth plurality of devices with respect to a horizontal surface of the second carrier substrate;

placing the third plurality of devices on a third plurality of device regions on the first device substrate; and

placing the fourth plurality of devices on a fourth plurality of device regions on the second device substrate,

wherein the devices in the first plurality of devices and the devices in the third plurality of devices have different operational characteristics.

17. The method of claim 5 wherein the carrier substrate is a first carrier substrate, and wherein the method further comprises:

providing a third plurality of devices, a fourth plurality of devices, and open regions on a second carrier substrate;

tilting the third plurality and fourth plurality of devices with respect to a horizontal surface of the second carrier substrate;

placing the third plurality of tilted devices on a third plurality of device regions on the first device substrate so that devices already on the first device substrate are disposed in the open regions; and

placing the fourth plurality of tilted devices on a fourth plurality of device regions on the second device substrate so that devices already on the second device substrate are disposed in the open regions.

18. The method of claim 5 further comprising:

bonding the first plurality of tilted devices to the first plurality of device regions using a first bonding material; and

bonding the second plurality of tilted devices to the second plurality of device regions using a second bonding material,

wherein the first and second bonding materials include at least one of a diffusion bondable metal and solder.

19. The method of claim 5 further comprising:

bonding the first and second tilted device pluralities to the device regions on the first and second device substrates using a first bonding material;

providing a third plurality of devices and a fourth plurality of devices on a second carrier substrate;

tilting the third plurality and fourth plurality of devices with respect to a horizontal surface of the second carrier substrate;

bonding the third plurality of tilted devices to a third plurality of device regions on the first device substrate using a second bonding material; and

bonding the fourth plurality of tilted devices to a fourth plurality of device regions on the second device substrate using the second bonding material,

wherein the first bonding material has a higher bonding temperature than the second bonding material.

20. The method of claim 5 wherein the first and second device pluralities comprise optoelectronic devices.

21. The method of claim 5 wherein the formation substrate is crystalline.

22. The method of claim 5 wherein the first and second device pluralities are disposed in a device array, and wherein the device array comprises at least two groups of devices, each device group comprises at least one device from the first plurality of devices and at least one device from the second plurality of devices.

23. The method of claim 5 wherein the first and second device pluralities are disposed in a device array, and wherein the device array comprises at least two groups of devices, each device group comprises at least one device from the first plurality of devices and at least one device from the second plurality of devices, and wherein the method further comprises:

aligning the first device plurality with the first plurality of device regions; and

aligning the second device plurality with the second plurality of device regions, wherein aligning the second device plurality with the second plurality of device regions comprises shifting the carrier substrate a distance approximately equal to a dimension of a device in the array.

24. The method of claim 5,

wherein the first and second device pluralities are disposed in a device array, and wherein the device array comprises at least two groups of devices, each device group comprises at least one device from the first plurality of devices and at least one device from the second plurality of devices, and wherein each device group has a dimension Px and Py,

and wherein at least two adjacent device regions on the first device substrate are separated by a distance about equal to Px or Py.

25. The method of claim 5, wherein the devices in the first plurality of devices comprises VCSELs and photodetectors.

26. The method of claim 5, wherein devices within the first plurality of devices have different operational characteristics.

27. The method of claim 5,

wherein placing the first plurality of devices on the first plurality of device regions comprises simultaneously placing the devices in the first plurality of devices on the first plurality of device regions;

and

wherein placing the second plurality of devices on the second plurality of device regions comprises simultaneously placing the devices in the second plurality of devices on the second plurality of device regions.

28. The method of claim 5 wherein the device regions on the first device substrate correspond to the locations of input and output terminals of a chip to be mounted to the first device substrate, and wherein the first and second plurality of devices comprise at least one of a photodetector, a photodetector amplifier, a VCSEL, and a VCSEL driver.

29. The method of claim 5 further comprising:

bonding a chip to the first device substrate,

wherein the first plurality of device regions and the second plurality of device regions are at locations corresponding to input and output terminals of the chip.

30. The method of claim 5 further comprising:

bonding a chip to the first device substrate,

wherein at least some devices in the first plurality of devices are not disposed directly under an input or an output terminal of the chip disposed on the device assembly.

31. The method of claim 5 further comprising, after placing the first and second device pluralities on the first and second device substrates:

depositing a cover layer over the first and second device pluralities to embed the first and second device pluralities to form first and second device assemblies.

32. The method of claim 5 wherein at least two devices in the first and second device pluralities are operational at different radiation wavelengths.

33. The method of claim 5 further comprising:

forming a first plurality of waveguides on the first device substrate and forming a second plurality of waveguides on the second device substrate, wherein the waveguides communicate the devices in the first and second device pluralities.

34. The method of claim 5 wherein the first plurality of devices and the second plurality of devices include optical filters, wherein at least one optical filter includes a plurality of dielectric films or photonic crystals.

35. The method of claim 5 wherein the first plurality of devices and the second plurality of devices include a filter formed on an angled surface of a waveguide element.

36. The method of claim 5:

wherein the first and second device substrates comprise electrical circuitry.

37. The method of claim 36 wherein the first device assembly is a polymer smart pixel.

38. The method of claim 36 wherein the second device assembly is an interface chip layer.

39. The method of claim 5 further comprising:

depositing a polymeric cover layer on the first device substrate over the first device plurality; and

planarizing the cover layer.

40. The method of claim 5 further comprising:

depositing a polymeric cover layer on the first device substrate over the first device plurality; and

removing the first device substrate from the first device plurality.

41. The method of claim 5 further comprising:

mounting a chip on the first device substrate.

42. The method of claim 5 further comprising:

forming a waveguide on the first device substrate using a vapor deposition process.

43. The method of claim 5 further comprising, after placing the first plurality of devices on the first device substrate:

forming a first device assembly including the first plurality of devices and the first device substrate, wherein the first device assembly comprises at least one of an LSI chip, IC chip, optical circuitry, CSP or MCM.

44. The method of claim 5 further comprising, after placing the first plurality of devices on the first device substrate:

building up multiple layers on the first device substrate.

45. The method of claim 5 further comprising:

forming optical waveguides on the first device substrate.

46. The method of claim 5 further comprising mounting a chip on the first device substrate, wherein the device regions on the first device substrate correspond to the locations of input and output terminals of the chip mounted on the first device substrate.

47. The method of claim 5, wherein the first and second device substrates comprise at least one of an LSI chip, optical circuitry, CSP or MCM.

48. The method of claim 5 wherein said tilting is by a magnetic field application.

49. A method for forming an apparatus, the method comprising:

forming a first device assembly using the method of claim 5;

forming a second device assembly; and

forming an apparatus comprising the first and second device assemblies.

50. The method of claim 49 wherein forming the apparatus comprises laminating the first and second device assemblies to each other.

51. The method of claim 49 wherein the second device assembly is a multichip module or a chip scale package.

52. The method of claim 49 wherein the second device assembly is formed on the first device assembly using a build-up process.

53. A method for placing device pluralities on device substrates, the method comprising:

providing an array of devices on a carrier substrate having a generally horizontal surface, wherein the array comprises multiple device pluralities having devices in predetermined patterns;

tilting the device pluralities with respect to the generally horizontal surface of the carrier substrate; and

respectively placing the tilted device pluralities on device substrates having device regions in predetermined patterns corresponding to the predetermined patterns of the device pluralities.

54. The method of claim 53 further comprising:

bonding the tilted device pluralities to device regions on each of the device substrates using a bonding material.

55. The method of claim 53 further comprising, prior to placing:

respectively aligning the tilted device pluralities with the device regions on the respective device substrates, wherein each respective alignment comprises shifting the carrier substrate a distance approximately equal to N×

d, wherein d is approximately equal to a dimension of a device in the array or a pitch of the devices in the array, and wherein N is an integer of at least one.

56. The method of claim 53 wherein the array of devices includes groups of devices, wherein each group includes at least one device from each of the tilted device pluralities.

57. The method of claim 53 wherein the array comprises multiple device groups, each device group has dimensions Px and Py, and wherein adjacent device regions on the device substrates are separated by a distance Px or Py.

58. The method of claim 53 wherein the devices in each of the tilted device pluralities have the same pattern.

59. The method of claim 53 further comprising, prior to providing:

forming the array of devices on a formation substrate.

60. The method of claim 53 further comprising, prior to providing:

forming the array of devices on a formation substrate,

wherein the formation substrate comprises a semiconductor.

61. The method of claim 53 wherein the array of devices includes groups of devices, and each group includes at least one device from each of the tilted device pluralities;

and the device groups have a pitch in the array, wherein the device group pitch is equal to the pitch of the device regions each of the device substrates.

62. The method of claim 53 further comprising:

testing the array of devices for defective devices; and

not placing defective devices on the device substrates.

63. The method of claim 53 wherein the patterns formed by the device regions on each of the device substrates and the patterns formed by the devices in each of the tilted device pluralities are the same.

64. The method of claim 53 wherein said tilting is by a magnetic field application.

65. A method for placing device pluralities on device substrates, the method comprising:

providing an array of devices on a carrier substrate having a generally horizontal surface, wherein the array comprises multiple device pluralities having devices in predetermined patterns;

tilting the device pluralities with respect to the generally horizontal surface of the carrier substrate; and

respectively placing the device pluralities on predetermined patterns of device regions corresponding to the predetermined patterns of the device pluralities.

66. The method of claim 65 wherein the predetermined patterns of device regions are respectively disposed on different device substrates.

67. The method of claim 65 wherein the predetermined patterns of device regions are on the same device substrate.