Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof

• US 6,670,234 B2
• Filed: 06/22/2001
• Issued: 12/30/2003
• Est. Priority Date: 06/22/2001
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Radens, Carl J., Wang, Li-Kong
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US09/887,403
• Publication Number:
  US 20020197792A1
• Time in Patent Office: 921 Days
• Field of Search: 438/214, 438/227, 438/246
• US Class Current: 438/246
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells.

Claims

1. A method for fabricating dynamic random access memory (DRAM) and flash memory cells on a single chip, comprising the steps of:

providing a silicon substrate;

forming a trench capacitor for each of the DRAM cells in the silicon substrate;

forming isolation regions in the silicon substrate, the isolation regions being electrically isolated from each other;

forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions;

forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, wherein the first and second type wells for the DRAM cells are connected to a corresponding trench capacitor for the DRAM cell;

forming a buried capacitor plate in the silicon substrate, the buried capacitor plate being connected to the trench capacitor;

forming a first type band in the silicon substrate, the first type band being connected between the buried capacitor plate and the first type well for the DRAM cell;

forming oxide layers for DRAM and flash memory cells on the second type wells;

forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells; and

forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, the source and drain regions being associated with each of the gate electrodes for DRAM and flash memory cells.

2. The method of claim 1, wherein the isolation regions are shallow trench isolation regions having depth in a range from about 100 nm to about 500 nm.

3. The method of claim 1, wherein the trench capacitor has depth in a range from 6 μ

m to about 10 μ

m.

4. The method of claim 1, wherein forming the first type wells for DRAM and flash memory cells includes the steps of:

forming a mask layer having a first pattern on the silicon substrate;

partially removing the mask layer in accordance with the first pattern; and

performing ion implantation with the first type impurity in the first predetermined regions where the mask layer is removed.

5. The method of claim 4, wherein the first type wells are n-wells and the first type impurity is n-conductivity type impurity.

6. The method of claim 4, wherein the trench capacitor is connected to a corresponding first type well for a DRAM cell.

7. The method of claim 4, wherein forming the second type wells for DRAM and flash memory cells includes the steps of:

removing the mask layer having the first pattern from the silicon substrate;

forming a mask layer having a second pattern on the silicon substrate;

partially removing the mask layer in accordance with the second pattern; and

performing ion implantation with the second type impurity in the second predetermined regions where the mask layer is removed.

8. The method of claim 7, wherein the second type wells are p-wells and the second type impurity is p-conductivity type impurity.

11. The method of claim 1, wherein forming the oxide layers for DRAM and flash memory cells includes performing ion implantation of nitrogen to retard oxidation in regions where the oxide layers are formed so that the oxide layers have a predetermined thickness.

12. The method of claim 11, wherein the oxide layers for DRAM and flash memory cells have thickness in a range from about 3 nm to about 10 nm.

13. The method of claim 1, further including the steps of:

forming first type wells for support devices in the silicon substrate by implanting the first type impurity;

forming second type wells for support devices in the silicon substrate by implanting the second type impurity; and

forming oxide layers for support devices on the first and second type wells for support devices.

14. The method of claim 13, further including performing ion implantation of nitrogen to retard oxidation in regions where the oxide layers for support devices are formed so that the oxide layers for support devices have a predetermined thickness.

15. The method of claim 14, wherein the oxide layers for support devices includes thin oxide layers having thickness in a range from about 2 nm to about 5 nm and thick oxide layers having thickness in a range from about 3 nm to about 20 nm.

16. The method of claim 13 further including the steps of:

forming gate electrodes for support devices on the oxide layers for support devices; and

forming source and drain regions for support devices in the first and second type wells for support devices, the source and drain regions for support devices being associated with each of the gate electrodes for support devices.

17. The method of claim 16, further including forming sidewall spacers on sidewalls of each of the gate electrodes for DRAM and flash memory cells and support devices.

18. The method of claim 16, wherein the source and drain regions associated with each of the gate electrodes for DRAM and flash memory cells and support devices are self-aligned silicide.

19. The method of claim 16, wherein the first type wells for DRAM and flash memory cells and the first type wells for support devices are formed at a substantially same time;

the second type well for DRAM and flash memory cells and the second type well for support devices are formed at a substantially same time;

the gate electrodes for DRAM and flash memory cells and the gate electrodes for support devices are formed at a substantially same time; and

the oxide layers for DRAM and flash memory cells and the oxide layers for support devices are formed at a substantially same time.

9. A method for fabricating dynamic random access memory (DRAM) and flash memory cells on a single chip, comprising the steps of:

providing a silicon substrate;

forming a trench capacitor for each of the DRAM cells in the silicon substrate;

forming isolation regions in the silicon substrate, the isolation regions being electrically isolated from each other;

forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions;

forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions;

forming a first type band in the silicon substrate, the first type band being connected between a buried capacitor plate connected to the trench capacitor and the first type well for the DRAM cell, wherein forming the first type band includes the steps of;

forming a mask layer having a third pattern on the silicon substrate;

partially removing the mask layer in accordance with the third pattern; and

performing ion implantation with the first type impurity in regions where the mask layer is removed;

forming oxide layers for DRAM and flash memory cells on the second type wells;

forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells; and

forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, the source and drain regions being associated with each of the gate electrodes for DRAM and flash memory cells.

10. The method of claim 9, wherein the first type well and the first type band have n-conductivity impurity and the second type well has p-conductivity impurity.