Non-volatile memory cell having bilayered floating gate and fabricating method thereof
First Claim
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1. A method for forming a non-volatile memory cell, comprising the steps of:
- (a) forming a tunnel oxide layer on a first conductivity type semiconductor substrate;
(b) forming first polysilicon layer lines longitudinally arranged in a bit line direction and separated from each other by a predetermined distance on the tunnel oxide layer;
(c) forming source and drain regions by implanting second conductivity type impurity ions in the semiconductor substrate restricted by the first polysilicon layer lines;
(d) forming first polysilicon layer patterns in the form of islands by patterning the first polysilicon layer lines;
(e) forming buried oxide layers for filling spaces between the first polysilicon layer patterns, wherein forming the buried oxide layers comprises forming an oxide layer on the first polysilicon layer patterns and the exposed tunnel oxide layer and flattening the oxide layer using an etch back process so that the upper side surfaces of the first polysilicon layer patterns are exposed;
(f) forming second polysilicon layer lines longitudinally arranged in the bit line direction to be separated from each other on the buried oxide layers and the first polysilicon layer patterns so that the second polysilicon layer lines completely cover the first polysilicon layer patterns, wherein the first and second polysilicon layer lines are used in forming a bilayered floating gate structure;
(g) forming an interlayer dielectric layer on the exposed surfaces of the second polysilicon layer lines and the buried oxide layers;
(h) forming third polysilicon layer patterns longitudinally arranged in a word line direction on the interlayer dielectric layer so that the third polysilicon layer patterns completely overlap the first polysilicon layer patterns and partially overlap the second polysilicon layer lines such that portions of the second polysilicon layer lines are exposed and not covered by the third polysilicon layer patterns; and
(i) after forming the third polysilicon layer patterns, sequentially removing the interlayer dielectric layer and the portions of the second polysilicon layer lines exposed by the third polysilicon layer patterns.
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Abstract
A non-volatile memory cell is provided. The non-volatile memory cell includes a first conductivity type semiconductor substrate, second conductivity type source/drain regions longitudinally arranged in a direction to be parallel to each other and separated from each other by a predetermined distance in the semiconductor substrate, such that the second conductive source/drain regions define a channel region therebetween. A tunnel oxide layer is formed on the semiconductor substrate. First conductive layer patterns are formed on the tunnel oxide layer on the channel formation region in the form of islands. Buried oxide layers fill spaces between the adjacent first conductive layer patterns. Second conductive layer patterns are formed on the upper surfaces and the upper side surfaces of the first conductive layer patterns and arranged so that their edges are extended to some surfaces of the buried oxide layers. An interlayer dielectric layer is formed on the second conductive layer patterns, and third conductive layer patterns are arranged to be vertical to the source/drain regions on the interlayer dielectric layer patterns.
18 Citations
6 Claims
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1. A method for forming a non-volatile memory cell, comprising the steps of:
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(a) forming a tunnel oxide layer on a first conductivity type semiconductor substrate;
(b) forming first polysilicon layer lines longitudinally arranged in a bit line direction and separated from each other by a predetermined distance on the tunnel oxide layer;
(c) forming source and drain regions by implanting second conductivity type impurity ions in the semiconductor substrate restricted by the first polysilicon layer lines;
(d) forming first polysilicon layer patterns in the form of islands by patterning the first polysilicon layer lines;
(e) forming buried oxide layers for filling spaces between the first polysilicon layer patterns, wherein forming the buried oxide layers comprises forming an oxide layer on the first polysilicon layer patterns and the exposed tunnel oxide layer and flattening the oxide layer using an etch back process so that the upper side surfaces of the first polysilicon layer patterns are exposed;
(f) forming second polysilicon layer lines longitudinally arranged in the bit line direction to be separated from each other on the buried oxide layers and the first polysilicon layer patterns so that the second polysilicon layer lines completely cover the first polysilicon layer patterns, wherein the first and second polysilicon layer lines are used in forming a bilayered floating gate structure;
(g) forming an interlayer dielectric layer on the exposed surfaces of the second polysilicon layer lines and the buried oxide layers;
(h) forming third polysilicon layer patterns longitudinally arranged in a word line direction on the interlayer dielectric layer so that the third polysilicon layer patterns completely overlap the first polysilicon layer patterns and partially overlap the second polysilicon layer lines such that portions of the second polysilicon layer lines are exposed and not covered by the third polysilicon layer patterns; and
(i) after forming the third polysilicon layer patterns, sequentially removing the interlayer dielectric layer and the portions of the second polysilicon layer lines exposed by the third polysilicon layer patterns. - View Dependent Claims (2, 3, 4, 5, 6)
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Current AssigneeSamsung Electronics Co. Ltd.
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Original AssigneeSamsung Electronics Co. Ltd.
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InventorsYoon, Ki-chang
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Primary Examiner(s)Smith, Matthew
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Assistant Examiner(s)Malsawma, Lex H.
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Application NumberUS09/791,910Publication NumberTime in Patent Office1,041 DaysField of Search438/259, 438/257, 438/264, 438/283, 438/593, 438/592, 438/596, 438/201, 438/211, 257/314, 257/315, 257/316, 257/317, 257/321US Class Current438/257CPC Class CodesH10B 41/30 characterised by the memory...H10B 69/00 Erasable-and-programmable R...
