High-pressure anneal process for integrated circuits

• US 6,670,289 B2
• Filed: 05/17/2002
• Issued: 12/30/2003
• Est. Priority Date: 01/22/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lane, Richard H., Wald, Phillip G.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Kilday, Lisa
• Application Number:
  US10/150,319
• Publication Number:
  US 20020127885A1
• Time in Patent Office: 592 Days
• Field of Search: 438/17, 438/149, 438/660, 438/661, 438/662, 438/663, 438/795
• US Class Current: 438/795
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: Y10S 438/904 Charge carrier lifetime control
• CPC Class Codes: Y10S 438/908 Utilizing cluster apparatus

Abstract

This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Claims

1. A method for affecting a factor for determining at least a part of a threshold voltage for a transistor in a semiconductor device during an anneal process in a chamber, said transistor having at least one transistor gate structure including a silicon oxide layer and having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof, and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor device, said method comprising:

exerting a diffusion pressure on said transistor, said diffusion pressure in said chamber higher than a prevailing ambient atmospheric pressure outside said chamber during said anneal process;

exposing said transistor having at least one transistor gate structure including a silicon oxide layer and having a film of silicon nitride used as at least one of a sidewall spacer and a capping layer for a field-effect transistor gate located on a portion thereof, and having a silicon nitride film deposited as a final layer over at least a portion of said semiconductor device, to a hydrogen-containing atmosphere during said exerting a diffusion pressure in said chamber, wherein said diffusion pressure has a partial pressure of hydrogen within said hydrogen-containing atmosphere of a minimum of 20 percent of the total pressure; and

dissipating a charge trapped in relation to said silicon oxide layer using hydrogen from said hydrogen-containing atmosphere.

2. The method in claim 1, wherein said dissipating a charge comprises diffusing hydrogen from said hydrogen-containing atmosphere in said chamber throughout said silicon oxide layer.

3. The method in claim 2, wherein:

said exerting a diffusion pressure on said transistor comprises exerting a diffusion pressure on a transistor, including an overlying layer at least partially covering said silicon oxide layer; and

diffusing hydrogen from said hydrogen-containing atmosphere in said chamber through said overlying layer to said silicon oxide layer.