Semiconductor device and method for manufacturing semiconductor device

• US 6,670,673 B2
• Filed: 04/10/2002
• Issued: 12/30/2003
• Est. Priority Date: 04/18/2001
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Sakakibara, Jun
• Primary Examiner(s): Thompson, Craig
• Application Number:
  US10/118,930
• Publication Number:
  US 20020155685A1
• Time in Patent Office: 629 Days
• Field of Search: 257/107, 257/328, 257/329, 257/335, 257/336, 257/341, 257/491, 257/492
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A first trench is formed in a surface of an n⁺-type semiconductor substrate that forms a source region. A p-type base region, an n⁻-type drift region, and an n⁺-type drain region are deposited in this order in the first trench using epitaxial growth. A second trench extending from the source region to the drift region through the base region is formed in the surface. A gate insulating film and a gate electrode are formed on a surface defining the second trench. The n⁺-type drain region has a location where growing surfaces come together in epitaxial growth and where a defect is likely to occur, and the gate electrode lacks such a location and thus avoids an increase in normalized ON resistance. Therefore, the breakdown voltage remains high without increasing the ON resistance.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a top surface and a back surface, wherein the back surface is opposite to the top surface;

a source region of a first conduction type, which extends in the substrate perpendicularly from the top surface;

a base region of a second conduction type, which extends perpendicularly from the top surface, wherein the base region has a first surface and a second surface, the second surface being opposite to the first surface, wherein the first surface of the base region contacts the source region;

a drift region of the first conduction type, wherein the drift region has an impurity concentration lower than that of the source region and extends perpendicularly from the top surface and contacts the second surface of the base region;

a drain region extending perpendicularly from the top surface in the drift region;

a gate insulating film formed on a surface that defines a trench, wherein the gate insulating film extends perpendicularly from the top surface and extends in a lateral direction from the source region to the drift region through the base region; and

a gate electrode formed on a surface of the gate insulating film such that, when a voltage is applied to the gate electrode, a channel region is generated in the vicinity of a surface of the base region adjacent to the trench, wherein the flow of the channel occurs in the lateral direction.

2. The semiconductor device of claim 1, wherein the drain region is an epitaxially grown layer of the first conduction type in which two opposed parts of the grown layer have met one another.

3. The semiconductor device of claim 1, wherein the drain region, the drift region, and the base region have substantially homogeneous impurity concentrations in the perpendicular and the lateral directions.

4. The semiconductor device of claim 1 further comprising a metal layer, which is embedded at a boundary between the source region and the base region to electrically connect the source region and the base region.

5. The semiconductor device of claim 1 further comprising:

a first metal layer extending perpendicularly from the top surface to approximately the depth of the drain region at a boundary between the source region and the base region to electrically connect the source region and the base region; and

a second metal layer extending perpendicularly in the drain region from the top surface to approximately the depth of the drain region.

6. The semiconductor device of claim 1 further comprising a metal film formed on the back surface to electrically connect the source region and the base region.

7. The semiconductor device of claim 1, wherein the base region, the drift region, the drain region, the gate insulating film, and the gate electrode are parts of a cell, and the cell is one of a plurality of similar cells, and a drain electrode is connected to the drain region of each cell to form a plurality of transistors in a chip.

8. A semiconductor device comprising:

a semiconductor substrate having a top surface and a back surface, wherein the back surface is opposite to the top surface;

a source region of a first conduction type, which extends in the substrate perpendicularly from the top surface;

a base region of a second conduction type, which extends perpendicularly from the top surface, wherein the base region has a first surface and a second surface, the second surface being opposite to the first surface, wherein the first surface of the base region contacts the source region;

a drift region of the first conduction type, wherein the drift region has an impurity concentration lower than that of the source region and extends perpendicularly from the top surface and contacts the second surface of the base region;

a drain region extending perpendicularly from the top surface in the drift region;

a gate insulating film formed on a surface that defines a trench, wherein the gate insulating film extends perpendicularly from the top surface and extends in a lateral direction from the source region to the drift region through the base region;

a gate electrode formed on a surface of the gate insulating film; and

at least one RESURF layer of the second conduction type, wherein the RESURF layer extends perpendicularly from the top surface in the drift region such that, when a voltage is applied to the gate electrode, a channel region is generated in the vicinity of a surface of the base region adjacent to the trench, wherein the flow of the channel occurs in the lateral direction.

9. The semiconductor device of claim 8, wherein the drain region, the drift region, the base region, and the RESURF layer have homogeneous impurity concentrations in the perpendicular and the lateral directions.

10. The semiconductor device of claim 8, wherein the RESURF layer is one of a plurality of RESURF layers, which are formed to completely deplete the drift region with depletion layers formed respectively about the RESURF layers when the voltage is not applied to the gate electrode.

11. The semiconductor device of claim 8, wherein the RESURF layer contacts the base region.