Oscillator tuning method

• US 6,670,852 B1
• Filed: 10/17/2001
• Issued: 12/30/2003
• Est. Priority Date: 10/17/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Hauck, Lane T.
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/981,448
• Time in Patent Office: 804 Days
• Field of Search: 331/17, 331/1.A, 331/176, 331/44, 327/159, 327/156, 327/160
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/148 said digital means comprising a counter or a divider

Abstract

An apparatus comprising an output circuit and a control circuit. The output circuit may be configured to generate an output signal oscillating at a frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to (i) a frequency of said input signal when in a first mode and (ii) a stored value when in a second mode.

Claims

1. An apparatus comprising:

a first circuit configured to generate an output signal oscillating at a first frequency in response to a first control signal; and

a second circuit configured to (a) receive a calibration signal oscillating at a second frequency and (b) generate said first control signal in response to (i) a counter value when in a first mode and (ii) a stored value when in a second mode, wherein, while in said first mode, said counter value is adjusted in response to a difference between said first frequency and said second frequency.

2. The apparatus according to claim 1, wherein said stored value is calibrated when said apparatus is in said first mode.

3. The apparatus according to claim 1, wherein said first circuit comprises a digitally tuned oscillator.

4. The apparatus according to claim 1, wherein said counter value is adjusted in response to a phase difference between said output signal and said calibration signal.

5. The apparatus according to claim 4, wherein said second circuit is further configured to generate a detect signal in response to said phase difference.

6. The apparatus according to claim 5, further comprising a logic circuit configured to replace said stored value with said counter value in response to said detect signal.

7. The apparatus according to claim 1, wherein said second mode comprises a normal operation mode and said first mode comprises a calibration mode.

8. The apparatus according to claim 1, wherein said second circuit comprises:

a phase detector configured to generate a detect signal in response to said calibration signal and said output signal.

9. The apparatus according to claim 8, wherein said second circuit further comprises:

a logic circuit configured to generate a plurality of second control signals in response to said input signal and said detect signal; and

a counter configured to generate said counter value in response to at least one of said plurality of second control signals.

10. The apparatus according to claim 1, wherein said second circuit is configured to generate said first control signal such that said first frequency is a multiple of said second frequency.

21. The apparatus according to claim 9, wherein said second circuit further comprises:

a memory configured to (i) present said stored value and (ii) store said counter value in response to one of said plurality of second control signals; and

a multiplexer configured to select either said counter value or said stored value as said control signal in response to one of said plurality of second control signals.

22. The apparatus according to claim 21, wherein said memory is non-volatile.

23. The apparatus according to claim 1, wherein said counter value is frozen when said first frequency and said second frequency are substantially the same.

11. An apparatus comprising:

means for generating an output signal oscillating at a first frequency in response to a control signal; and

means for generating said control signal in response to (i) a counter value when in a first mode and (ii) a stored value when in a second mode, wherein, while in said first mode, said counter value is adjusted in response to a difference between said first frequency and a second frequency of a calibration signal.

12. A method for tuning an oscillator, comprising the steps of:

(A) detecting the presence of an input signal oscillating at a first frequency;

(B) generating an output signal oscillating at a second frequency in response to a control signal; and

(C) calibrating said control signal when said input signal is present in response to a counter value, wherein said counter value is adjusted in response to a difference between said first frequency and said second frequency.

13. The method according to claim 12, wherein step (C) further comprises:

setting an initial value for said counter value.

14. The method according to claim 13, wherein step (C) further comprises:

passing said initial value to a frequency generator.

15. The method according to claim 12, wherein step (C) further comprises:

increasing said counter value when said first frequency of said input signal is greater than said second frequency of said output signal.

16. The method according to claim 12, wherein step (C) further comprises:

decreasing said counter value when said first frequency of said input signal is less than said second frequency of said output signal.

17. The method according to claim 12, wherein step (C) further comprises:

determining whether said first frequency of said input signal is substantially the same as said second frequency of said output signal.

18. The method according to claim 12, wherein step (C) further comprises:

freezing said counter value when a phase of said input signal and a phase of said output signal are substantially the same.

19. The method according to claim 18, wherein step (C) further comprises:

storing said counter value to a non-volatile memory.

20. The method according to claim 19, wherein step (C) further comprises:

generating said control signal from said stored value.