High speed voltage-controlled ring oscillator

• US 6,670,858 B2
• Filed: 11/01/2001
• Issued: 12/30/2003
• Est. Priority Date: 11/01/2000
• Status: Expired due to Term

• Current Assignee: Goldcup 5514 Ab Unat Tyco Electronics Svenska Holdings AB, Mobix Labs, Inc.
• Original Assignee: Primarion Incorporated (Infineon Technologies AG)
• Inventors: Tang, Benjamim
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Chang, Joseph
• Application Number:
  US10/004,364
• Publication Number:
  US 20020097098A1
• Time in Patent Office: 789 Days
• Field of Search: 331/57, 331/34, 331/42, 331/177.R, 327/538
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/03 Astable circuits
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/189 comprising a D/A converter for generating a coarse tuning voltage

Abstract

A high speed ring voltage-controlled oscillator (VCO) system is provided. The ring VCO system includes a plurality of interpolation stages coupled in a “look-ahead” configuration. Each interpolation stage receives two signal inputs and outputs a single differential voltage representative of a time delay interpolation between the two input signals. In accordance with the invention, each interpolation stage receives a first signal input from the immediately previous stage and a second signal input from the output of a different stage. In this manner, the delay stages in the ring VCO can generate a variable delay by interpolating between inputs with small relative delays without adding additional delay to the total loop delay.

Claims

1. A voltage-controlled ring oscillator comprising:

a plurality of interpolation stages having two signal inputs and a signal output, each of said stages receiving a first signal input comprising an output from an immediate previous stage (X) and a second signal input comprising an output from a previous stage (X−

1); and

each of said stages adapted to receive first and second control voltages.

2. The voltage-controlled ring oscillator of claim 1, wherein each of said stages comprises an analog summer.

3. The voltage-controlled ring oscillator of claim 2 comprising CMOS architecture.

4. The voltage-controlled ring oscillator of claim 1 further comprising a voltage-to-current (V-I) translator in electrical communication with each of said stages.

5. The voltage-controlled ring oscillator of claim 4, wherein said V-I translator comprises an input port and two output ports.

6. The voltage-controlled ring oscillator of claim 2, further comprising a voltage-to-current (V-I) translator in electrical communication with each of said analog summers and providing a substantially constant voltage to said analog summer.

7. The voltage-controlled ring oscillator of claim 6, further comprising a voltage mirror coupled between said V-I translator and said analog summer.

8. The voltage-controlled ring oscillator of claim 2, wherein said analog summer receives said first and second signal inputs and one of said inputs being weight limited.

9. The voltage controlled ring oscillator of claim 8, wherein said weight limited input being less than 100%.

10. The voltage-controlled ring oscillator of claim 8, wherein said weight limited input being limited to 80%.

11. A delay interpolation voltage-controlled oscillator (VCO) comprising:

a plurality of analog summers coupled in a look-ahead interpolation configuration comprising;

a first analog summer having a first input (A) and a second input (B) and an output (C);

a second analog summer having a first input (B) and a second input (C) and an output (D);

a third analog summer having a first input (C) and a second input (D) and an output (A);

a fourth analog summer having a first input (D) and a second input (A) and an output (B),

whereby, each of said analog summers outputs is electrically coupled as inputs to the other analog summers; and

at least two control voltages supplied to each of said plurality of analog summers.

12. The VCO of claim 11, wherein a weight of one of said inputs to at least one of said analog summers is limited.

13. The VCO of claim 12, wherein said weight limited input is less than 100%.

14. The VCO of claim 12, wherein said weight limited input is 80%.

15. The VCO of claim 11, further comprising a voltage to current translator providing a constant voltage to said plurality of analog summers.

16. A voltage-controlled ring oscillator comprising:

a plurality of interpolation stages coupled in a look-ahead interpolation architecture such that each of said stages includes a first and second signal input and a signal output, said first signal input comprising an output from an immediate previous stage (X) and said second signal input comprising an output from a previous stage (X−

1), one of said signal inputs being weight limited to less than 100%; and

at least two control voltages supplied to each of said stages.

17. The voltage-controlled ring oscillator of claim 16, wherein said weight limited input comprises 80%.

18. The voltage-controlled ring oscillator of claim 16, wherein each of said stages comprises an analog summer.

19. The voltage-controlled ring oscillator of claim 16, further comprising a voltage-to-current (V-I) translator in electrical communication with each of said stages.

20. The voltage-controlled ring oscillator of claim 19, wherein said V-I translator provides a substantially constant voltage to each of said stages.

21. A method for signal interpolation in a voltage-controlled oscillator (VCO) comprising a plurality of interpolation stages, said method comprising the steps of:

applying a first control voltage to an interpolation stage (N) of said plurality of interpolation stages;

applying a second control voltage to an interpolation stage (N) of said plurality of interpolation stages;

applying a first signal input to said stage (N) such that said first signal comprises an output of a stage (N−

1);

applying a second signal input to said stage (N) such that said second signal comprises an output of a stag (N−

2);

using analog summation, determining a voltage representation of a time delay between said first and second signal;

outputting said voltage representation from said stage (N); and

repeating said method steps for each of said stages in said VCO.

22. The method for signal interpolation of claim 21, further comprising the step of weight limiting one of said first or second signal inputs.

23. The method for signal interpolation of claim 22, wherein said weight limiting step comprises limiting to 80%.

24. The method for signal interpolation of claim 21, wherein said step of applying a control voltage comprises the steps of:

applying a differential voltage to a voltage-to-current (V-I) translator;

outputting two differential voltages from said (V-I) translator; and

applying said two differential voltages to two control inputs of said stage.

25. The method for signal interpolation of claim 24, further comprising the step of generating two differential voltages such that when applied to said two control inputs of said stage, a substantially constant current is received.

26. The method for signal interpolation of claim 24, wherein said step of applying a control voltage further comprises the step of applying a control voltage to a third control input such that a substantially fixed current is received.

27. A voltage-controlled ring oscillator comprising:

a plurality of interpolation stages having two signal inputs and a signal output, each of said stages receiving a first signal input comprising an output from an immediate previous stage (X) and a second signal input comprising an output from a previous stage (X−

1);

a control voltage supplied to each of said stages; and

a voltage-to-current (V-I) translator in electrical communication with each of said stages.

28. The voltage-controlled ring oscillator of claim 27, wherein said V-I translator comprises an input port and two output ports.

31. The voltage-controlled ring oscillator of claim 27, wherein each of said stages comprises an analog summer and said analog summer receives said first and second signal inputs and one of said inputs being weight limited.

32. The voltage-controlled ring oscillator of claim 31, wherein said weight limited input being limited to less than 100%.

33. The voltage-controlled ring oscillator of claim 31, wherein said weight limited input being limited to 80%.

29. A voltage-controlled ring oscillator comprising:

a plurality of interpolation stages having two signal inputs and a signal output, each of said stages receiving a first signal input comprising an output from an immediate previous stage (X) and a second signal input comprising an output from a previous stage (X−

1);

a control voltage supplied to each of said stages;

wherein each of said stages comprises an analog summer; and

a voltage-to-current (V-I) translator in electrical communication with each of said analog summers and providing a substantially constant voltage to said analog summers.

30. The voltage-controlled ring oscillator of claim 29, further comprising a voltage mirror coupled between said V-I translator and said analog summer.

34. A delay interpolation voltage-controlled oscillator (VCO) comprising:

a plurality of analog summers coupled in a look-ahead interpolation configuration comprising;

a first analog summer having a first input (A) and a second input (B) and an output (C);

a second analog summer having a first input (B) and a second input (C) and an output (D);

a third analog summer having a first input (C) and a second input (D) and an output (A);

a fourth analog summer having a first input (D) and a second input (A) and an output (B),

whereby, each of said analog summers outputs is electrically coupled as inputs to the other analog summers; and

a control voltage supplied to said plurality of analog summers;

wherein a weight of one of said inputs to at least one of said analog summers is limited; and

said weight limited input is 80%.

35. A delay interpolation voltage-controlled oscillator (VCO) comprising:

a plurality of analog summers coupled in a look-ahead interpolation configuration comprising;

a first analog summer having a first input (A) and a second input (B) and an output (C);

a second analog summer having a first input (B) and a second input (C) and an output (D);

a third analog summer having a first input (C) and a second input (D) and an output (A);

a fourth analog summer having a first input (D) and a second input (A) and an output (B),

whereby, each of said analog summers outputs is electrically coupled as inputs to the other analog summers;

a control voltage supplied to said plurality of analog summers; and

a voltage to current translator providing a constant voltage to said plurality of analog summers.

36. A voltage-controlled ring oscillator comprising:

a plurality of interpolation stages coupled in a look-ahead interpolation architecture such that each of said stages includes a first and second signal input and a signal output, said first signal input comprising an output from an immediate previous stage (X) and said second signal input comprising an output from a previous stage (X−

1), one of said signal inputs being weight limited to less than 100%; and

a control voltage supplied to each of said stages;

wherein said weight limited input comprises 80%.

37. A voltage-controlled ring oscillator comprising:

a plurality of interpolation stages coupled in a look-ahead interpolation architecture such that each of said stages includes a first and second signal input and a signal output, said first signal input comprising an output from an immediate previous stage (X) and said second signal input comprising an output from a previous stage (X−

1), one of said signal inputs being weight limited to less than 100%;

a control voltage supplied to each of said stages; and

a voltage-to-current (V-I) translator in electrical communication with each of said stages.

38. The voltage-controlled ring oscillator of claim 37, wherein said V-I translator provides a substantially constant voltage to each of said stages.

39. A method for signal interpolation in a voltage-controlled oscillator (VCO) comprising a plurality of interpolation stages, said method comprising the steps of:

applying a control voltage to an interpolation stage (N) of said plurality of interpolation stages;

applying a first signal input to said stage (N) such that said first signal comprises an output of a stage (N−

1);

applying a second signal input to said stage (N) such that said second signal comprises an output of a stage (N−

2);

using analog summation, determining a voltage representation of a time delay between said first and second signal;

outputting said voltage representation from said stage (N);

repeating said method steps for each of said stages in said VCO; and

weight limiting one of said first or second signal inputs;

wherein said weight limiting step comprises limiting to 80%.

40. A method for signal interpolation in a voltage-controlled oscillator (VCO) comprising a plurality of interpolation stages, said method comprising the steps of:

applying a control voltage to an interpolation stage (N) of said plurality of interpolation stages;

applying a first signal input to said stage (N) such that said first signal comprises an output of a stage (N−

1);

applying a second signal input to said stage (N) such that said second signal comprises an output of a stage (N−

2);

using analog summation, determining a voltage representation of a time delay between said first and second signal;

outputting said voltage representation from said stage (N); and

repeating said method steps for each of said stages in said VCO;

wherein said step of applying a control voltage comprises the steps of;

applying a differential voltage to a voltage-to-current (V-I) translator;

outputting two differential voltages from said (V-I) translator; and

applying said two differential voltages to two control inputs of said stage.

41. The method for signal interpolation of claim 40, further comprising the step of generating two differential voltages such that when applied to said two control inputs of said stage, a substantially constant current is received.

42. The method for signal interpolation of claim 40, wherein said step of applying a control voltage further comprises the step of applying a control voltage to a third control input such that a substantially fixed current is received.