Method for writing data into a semiconductor memory device and semiconductor memory therefor

• US 6,671,201 B2
• Filed: 04/01/2002
• Issued: 12/30/2003
• Est. Priority Date: 04/02/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Masuda, Kengo
• Primary Examiner(s): Tran, M.
• Application Number:
  US10/113,192
• Publication Number:
  US 20030185043A1
• Time in Patent Office: 638 Days
• Field of Search: 365/154, 365/202
• US Class Current: 365/154
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A method of writing data into a semiconductor memory device including a memory cell to which a power supply potential and a ground potential are provided is disclosed. The method may include generating a negative voltage (GNDL) lower than the ground potential and providing complementary data signals to a bit line pair when writing data to a memory cell wherein the low one of the complementary data signals is essentially the negative voltage. In this way, compensation for a potential increment which may be caused due to a wiring resistance, or the like, of a bit line (BL1) may be provided.

Claims

1. A method of writing data into a semiconductor memory device including a memory cell to which a positive power supply potential and a ground potential are provided and the memory cell is coupled to a first and second bit line, comprising the steps of:

generating a negative voltage lower than the ground potential; and

providing complementary data signals to the first and second bit lines when writing data to the memory cell wherein the low potential one of the complementary data signals is essentially the negative voltage.

2. The method of writing data into a semiconductor memory device according to claim 1, wherein:

the memory cell includes a transfer gate that is turned on when data is being written to the memory cell and then turned off after the writing of data is completed; and

a precharge potential is applied to the first and second bit lines after the transfer gate is turned off.

3. The method of writing data into a semiconductor memory device according to claim 2, wherein:

the precharge potential is essentially the positive power supply potential.

4. The method of writing data into a semiconductor memory device according to claim 1, wherein:

the negative voltage is less than or equal to a forward bias voltage of a PN junction.

5. The method of writing data into a semiconductor memory device according to claim 1, wherein:

the semiconductor memory device is a static random access memory.

6. The method of writing data into a semiconductor memory device according to claim 1, further including the step of:

providing the ground potential to the one of the first and second bit lines receiving the low one of the complementary data signals before providing the negative voltage.

7. A semiconductor memory device including a memory cell to which a power supply potential and a ground potential are provided and the memory cell is coupled to a first and second bit line, the semiconductor memory device comprising:

a voltage dropping circuit generating a negative voltage lower than the ground potential; and

a write circuit providing complementary data signals to the first and second bit lines when writing data to the memory cell wherein the low potential one of the complementary data signals is essentially the negative voltage.

8. The semiconductor memory device according to claim 7, wherein:

the memory cell includes a transfer gate that is turned on when data is being written to the memory cell and then turned off after the writing of data is completed; and

a precharge potential is applied to the first and second bit lines after the transfer gate is turned off.

9. The semiconductor memory device according to claim 8, wherein:

the precharge potential is essentially the power supply potential.

10. The semiconductor memory device according to claim 7, wherein:

the write circuit provides the ground potential to the one of the first and second bit lines receiving the low one of the complementary data signals before providing the negative voltage.

11. The semiconductor memory device according to claim 7, wherein the voltage dropping circuit includes:

a pulse delivering circuit providing a low pulse when writing data into the memory cell; and

a capacitor coupled to receive the low pulse and provide the negative voltage.

12. The semiconductor memory device according to claim 7, wherein:

the negative voltage is less than or equal to a forward bias voltage of a PN junction.

13. The semiconductor memory device according to claim 7, wherein:

the semiconductor memory device is a static random access memory.

14. A semiconductor memory device, comprising:

an array of memory cells arranged into rows and columns, each memory cell receiving a positive power supply potential and a ground potential;

each column of memory cells coupled to a first and second bit line; and

a write circuit providing complementary data signals to the first and second bit lines coupled to a first one of the columns of memory cells when writing data to a first memory cell in the first one of the columns of memory cells wherein the low potential one of the complementary data signals is a negative voltage below the ground potential.

15. The semiconductor memory device according to claim 14, wherein the write circuit includes:

a voltage dropping circuit providing the negative voltage to a predetermined one of the first and second bit lines coupled to the first one of the columns of memory cells in accordance with a data value to be written.

16. The semiconductor memory device according to claim 15, further including:

a selector circuit coupled between the write circuit and a plurality of the columns of memory cells to provide an electrical connection between the write circuit and the first one of the columns of memory cells during writing data to the first memory cell.

17. The semiconductor memory device according to claim 16, wherein:

the selector circuit provides the electrical connection in response to a predetermined address value.

18. The semiconductor memory device according to claim 14, wherein:

each of the memory cells include a first insulated gate field effect transistor (IGFET) coupled to the first bit line and a second IGFET coupled to the second bit line providing a data path to write data to the memory cell.

19. The semiconductor memory device according to claim 18, wherein:

each of the memory cells further include first and second inverters forming a latch for storing a data value.

20. The semiconductor memory device according to claim 19, wherein:

the first and second IGFETs are n-type IGFETs.