System, method and apparatus for pattern recognition with application to symbol recognition and regeneration for a caligraphic display

• US 6,671,406 B1
• Filed: 12/29/1999
• Issued: 12/30/2003
• Est. Priority Date: 12/29/1999
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Anderson, Bruce
• Primary Examiner(s): CHANG, JON CARLTON
• Application Number:
  US09/474,667
• Time in Patent Office: 1,462 Days
• Field of Search: 382/189, 382/181, 382/226, 382/227, 382/209, 382/217, 382/218, 345/204, 345/50, 345/51, 345/53, 345/87, 345/94, 345/98, 345/564, 345/566, 345/572, 345/14, 345/16, 345/17, 345/26
• US Class Current: 382/217
• CPC Class Codes: G06F 3/1475 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G06V 30/1985 Syntactic analysis, e.g. using a grammatical approach syntactic image representation G06V30/18171
• CPC Class Codes: G09G 1/07 with combined raster scan and calligraphic display

Abstract

The invention provides a technique for pattern recognition that employs a state machine that incorporates a sequence of table-look-up operations. A sequence of input parameters, which could be derived according to some application-specific algorithm, is used to generate a corresponding sequence of memory addresses that is used for the table-look-up operations. The memory tables are organized in a hierarchical, or tree-like, structure that corresponds to the input sequence. The table data is designed for the recognition of a specific set, or library, of input patterns. A given input sequence traces an input-specific path through the memory tables until one of the patterns in the library is recognized or until it is determined that the input sequence is inconsistent with any of the patterns in the library. For each pattern in the library, the table data is designed to accommodate the variations in the input values that are specific to the application (e.g., variations due to noise and/or tolerances). The input sequence is compared simultaneously to all of the patterns in the library, rather than being compared sequentially to only a single pattern at a time.

Claims

1. A display system apparatus comprising:

a display device comprising at least a two-dimensional array of display pixels;

at least one two-dimensional image memory that stores pixel values that reflect a specific display image;

refresh circuitry that refreshes said display device from said pixel values stored in said at least one two-dimensional image memory;

a signal input set comprised of at least one input signal wherein the variation over time of input values for said signal input set reflects symbols for display on said display device and wherein said signal input set comprises an analog X deflection input, an analog Y deflection input, and at least one video input signal;

a pattern recognition apparatus that recognizes the symbols of a first symbol set from said signal input set and further comprising an output that identifies recognized symbols of said first symbol set;

a rendering circuit that independently renders any of the symbols of a second symbol set into said at least one two-dimensional image memory;

a plurality of memory tables residing within at least one physical memory device;

addressing circuitry that derives a sequence of address values from said signal input set and applies said sequence of address values to address inputs of a corresponding sequence of memory tables from said plurality of memory tables to perform a sequence of memory table-look-up operations for producing a result that comprises said output that identifies recognized symbols of said first symbol set; and

interfacing circuitry that, in response to said output from said pattern recognition apparatus, commands the rendering of symbols from said second symbol set by said rendering circuitry.

2. The apparatus of claim 1, wherein said first symbol set and said second symbol set are the same.

3. The apparatus of claim 1 wherein said addressing circuitry further comprises:

first circuitry that converts time-sampled values of said analog X deflection input into a sequence of X digital values;

second circuitry that converts time-sampled values of said analog Y deflection input into a sequence of Y digital values; and

third circuitry that transforms said at least one video input signal and said sequence of X digital values and said sequence of Y digital values into said sequence of address values.

4. The apparatus of claim 3, wherein a set of data values is stored in said plurality of memory tables and wherein said set of data values reflects the expected sequences of address values for the case of said input values for said signal input set being a probable match to any symbol of said first symbol set.

5. The apparatus of claim 4, wherein said plurality of memory tables is organized into a structure of multiple levels having at least one of said plurality of memory tables at each of said multiple levels and wherein said sequence of memory tables progresses through said multiple levels of said structure.

6. The apparatus of claim 1, further comprising direct storage means that, when the variation over time of the input values of said signal input set reflects a symbol that is not recognized as being a symbol of said first symbol set, writes pixel values that are reflective of said at least one video input signal into at least one two-dimensional image memory at locations determined by said analog X deflection input and said analog Y deflection input.

7. A display system apparatus comprising:

a display device comprising at least a two-dimensional array of display pixels;

at least one two-dimensional image memory that stores pixel values that reflect a specific display image;

refresh circuitry that refreshes said display device from said pixel values stored in said at least one two-dimensional image memory;

a signal input set comprised of at least one input signal wherein the variation over time of input values for said signal input set reflects symbols for display on said display device wherein said signal input set comprises raster video;

a pattern recognition apparatus that recognizes the symbols of a first symbol set from said signal input set and further comprising an output that identifies recognized symbols of said first symbol set;

a rendering circuit that independently renders any of the symbols of a second symbol set into said at least one two-dimensional image memory;

a plurality of memory tables residing within at least one physical memory device;

addressing circuitry that derives a sequence of address values from said signal input set and applies said sequence of address values to address inputs of a corresponding sequence of memory tables from said plurality of memory tables to perform a sequence of memory table-look-up operations for producing a result that comprises said output that identifies recognized symbols of said first symbol set; and

interfacing circuitry that, in response to said output from said pattern recognition apparatus, commands the rendering of symbols from said second symbol set by said rendering circuitry.

8. The apparatus of claim 7, wherein said first symbol set and said second symbol set are the same.