System and method for dynamically sizing hardware loops and executing nested loops in a digital signal processor

• US 6,671,799 B1
• Filed: 08/31/2000
• Issued: 12/30/2003
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Parthasarathy, Sivagnanam
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/653,494
• Time in Patent Office: 1,216 Days
• Field of Search: 712/241, 712/230, 712/231, 712/245, 712/35, 712/36
• US Class Current: 712/241
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/381 Loop buffering

Abstract

There is disclosed, for use in a digital signal processor, an apparatus for dynamically sizing a hardware loop that executes a plurality of instruction sequences forming a plurality of instruction loops. The apparatus comprises: 1) N pairs of loop start registers and loop end registers, each loop start register for storing a loop start address and each loop end register for storing a loop end address; 2) N comparators, each of the N comparators associated with one of the N pairs of loop start registers and loop end registers, wherein each of the N comparators compares a selected one of a first loop start address and a first loop end address to a fetch program counter value to detect one of a loop start hit and a loop end hit; and 3) fetch address generation circuitry for detecting the loop start hit and the loop end hit and fetching from an address in a program memory an instruction associated with one of the loop start hit and the loop end hit and loading the fetched instruction into the hardware loop.

Claims

1. For use in a digital signal processor comprising an instruction fetch stage, a decode stage, a dispatch stage, and an execute stage, an apparatus for dynamically sizing a hardware loop capable of executing a plurality of instruction sequences forming a plurality of instruction loops comprising:

N pairs of loop start registers and loop end registers, each loop start register capable of storing a loop start address and each loop end register capable of storing a loop end address;

N comparators, each of said N comparators associated with one of said N pairs of loop start registers and loop end registers, wherein each of said N comparators is capable of comparing a selected one of a first loop start address and a first loop end address to a fetch program counter value to detect one of a loop start hit and a loop end hit; and

fetch address generation circuitry capable of detecting said loop start hit and said loop end hit and fetching from an address in a program memory an instruction associated with one of said loop start hit and said loop end hit and loading said fetched instruction into said hardware loop.

2. The apparatus for dynamically sizing a hardware loop as set forth in claim 1 wherein said N pairs of loop start registers and loop end registers comprise three pairs of loop start registers and loop end registers.

3. The apparatus for dynamically sizing a hardware loop as set forth in claim 2 wherein said three pairs of loop start registers and loop end registers comprise a first loop start register and a first loop end register associated with a first instruction loop, a second loop start register and a second loop end register associated with a second instruction loop, and a third loop start register and a third loop end register associated with a third instruction loop.

4. The apparatus for dynamically sizing a hardware loop as set forth in claim 3 further comprising a loop buffer having a loop buffer size M capable of storing M instructions.

5. The-apparatus for dynamically sizing a hardware loop as set forth in claim 4 further comprising a loop buffer comparator capable of comparing said loop buffer size M to a difference between a first loop start address and a first loop end address to determine if a selected instruction loop associated with said first loop start address and said first loop end address is capable of fitting in said loop buffer.

6. The apparatus for dynamically sizing a hardware loop as set forth in claim 5 wherein said loop buffer comparator performs said comparison whenever one of said loop start registers and said loop end registers is updated.

7. A digital signal processor comprising:

an instruction fetch stage;

a decode stage;

a dispatch stage;

an execution stage; and

an apparatus for dynamically sizing a hardware loop capable of executing a plurality of instruction sequences forming a plurality of instruction loops comprising;

N pairs of loop start registers and loop end registers, each loop start register capable of storing a loop start address and each loop end register capable of storing a loop end address;

N comparators, each of said N comparators associated with one of said N pairs of loop start registers and loop end registers, wherein each of said N comparators is capable of comparing a selected one of a first loop start address and a first loop end address to a fetch program counter value to detect one of a loop start hit and a loop end hit; and

fetch address generation circuitry capable of detecting said loop start hit and said loop end hit and fetching from an address in a program memory an instruction associated with one of said loop start hit and said loop end hit and loading said fetched instruction into said hardware loop.

8. The digital signal processor as set forth in claim 7 wherein said N pairs of loop start registers and loop end registers comprise three pairs of loop start registers and loop end registers.

9. The digital signal processor as set forth in claim 8 wherein said three pairs of loop start registers and loop end registers comprise a first loop start register and a first loop end register associated with a first instruction loop, a second loop start register and a second loop end register associated with a second instruction loop, and a third loop start register and a third loop end register associated with a third instruction loop.

10. The digital signal processor as set forth in claim 9 further comprising a loop buffer having a loop buffer size M capable of storing M instructions.

11. The digital signal processor as set forth in claim 10 further comprising a loop buffer comparator capable of comparing said loop buffer size M to a difference between a first loop start address and a first loop end address to determine if a selected instruction loop associated with said first loop start address and said first loop end address is capable of fitting in said loop buffer.

12. The digital signal processor as set forth in claim 11 wherein said loop buffer comparator performs said comparison whenever one of said loop start registers and said loop end registers is updated.

13. A wireless communication device comprising:

a radio frequency(RF) transceiver capable of receiving an incoming RF signal and down-converting said incoming RF signal to an incoming intermediate frequency (IF) signal;

analog processing circuitry capable of receiving said incoming IF signal and down-converting said incoming IF signal to an incoming digital data stream; and

a digital signal processor capable of receiving said incoming digital data stream and generating therefrom an analog baseband signal, said digital signal processor comprising;

an apparatus for dynamically sizing a hardware loop capable of executing a plurality of instruction sequences forming a plurality of instruction loops comprising;

N pairs of loop start registers and loop end registers, each loop start register capable of storing a loop start address and each loop end register capable of storing a loop end address;

N comparators, each of said N comparators associated with one of said N pairs of loop start registers and loop end registers, wherein each of said N comparators is capable of comparing a selected one of a first loop start address and a first loop end address to a fetch program counter value to detect one of a loop start hit and a loop end hit; and

fetch address generation circuitry capable of detecting said loop start hit and said loop end hit and fetching from an address in a program memory an instruction associated with one of said loop start hit and said loop end hit and loading said fetched instruction into said hardware loop.

14. The wireless communication device as set forth in claim 13 wherein said N pairs of loop start registers and loop end registers comprise three pairs of loop start registers and loop end registers.

15. The wireless communication device as set forth in claim 14 wherein said three pairs of loop start registers and loop end registers comprise a first loop start register and a first loop end register associated with a first instruction loop, a second loop start register and a second loop end register associated with a second instruction loop, and a third loop start register and a third loop end register associated with a third instruction loop.

16. The wireless communication device as set forth in claim 15 further comprising a loop buffer having a loop buffer size M capable of storing M instructions.

17. The wireless communication device as set forth in claim 16 further comprising a loop buffer comparator capable of comparing said loop buffer size M to a difference between a first loop start address and a first loop end address to determine if a selected instruction loop associated with said first loop start address and said first loop end address is capable of fitting in said loop buffer.

18. The wireless communication device as set forth in claim 17 wherein said loop buffer comparator performs said comparison whenever one of said loop start registers and said loop end registers is updated.

19. For use in a digital signal processor comprising an instruction fetch stage, a decode stage, a dispatch stage and an execute stage, a method of dynamically sizing a hardware loop capable of executing a plurality of instruction sequences forming a plurality of instruction loops comprising the steps of:

storing a loop start address and a loop end address in each of N pairs of loop start registers and loop end registers;

comparing in each of N comparators a selected one of a first loop start address and a first loop end address to a fetch program counter value to detect one of a loop start hit and a loop end hit, wherein the each of the N comparators is associated with one of the N pairs of loop start registers and loop end registers;

in response to detection of one of said loop start hit and said loop end hit, fetching from an address in a program memory an instruction associated with one of the loop start hit and the loop end hit; and

loading the fetched instruction into the hardware loop.

20. The method as set forth in claim 19 wherein the N pairs of loop start registers and loop end registers comprise three pairs of loop start registers and loop end registers.

21. The method as set forth in claim 20 wherein the three pairs of loop start registers and loop end registers comprise a first loop start-register and a first loop end register associated with a first instruction loop, a second loop start register and a second loop end register associated with a second instruction loop, and a third loop start register and a third loop end register associated with a third instruction loop.