Method and apparatus for simplifying a circuit model

• US 6,671,862 B1
• Filed: 08/07/2002
• Issued: 12/30/2003
• Est. Priority Date: 08/07/2002
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Seward, Robert Y.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Dinh, Paul
• Application Number:
  US10/213,960
• Time in Patent Office: 510 Days
• Field of Search: 716/1, 716/4-6, 716/10-13, 716/18, 703/14, 703/19
• US Class Current: 716/113
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method, apparatus, and computer program product are described for simplifying a circuit model. The circuit model has at least interconnected active device models, resistance models, and capacitance models. The method involves identifying an active device having an input at a first circuit node coupled to a resistance, where the resistance connects to a second circuit node of the circuit. An input capacitance of the active device is computed and a time constant is computed of the resistance and a total capacitance of the circuit node, including the input capacitance of the active device. The time constant is compared to a threshold, and, if the time constant is less than the threshold, the resistance is removed from the circuit model.

Claims

1. A method of simplifying a circuit model, the circuit model comprising a plurality of interconnected active device models, resistance models, and capacitance models, the method comprising the steps of:

identifying an active device having an input coupled to a first circuit node coupled to a resistance, where the resistance model is coupled to a second circuit node of the circuit model;

calculating an input capacitance of the active device;

computing a time constant of the resistance and a total capacitance of the first circuit node, where the total capacitance of the first circuit node includes the input capacitance of the active device;

comparing the time constant to a threshold; and

if the time constant is less than the threshold, removing the resistance from the circuit model and coupling the input of the active device to the second circuit node.

2. The method of claim 1, wherein the method is repeated for a plurality of active devices of the circuit model.

3. The method of claim 1, wherein the method is repeated at an input of the active device if the time constant was less than the threshold and, after removing the resistor from the circuit model and coupling the input of the active device to the second circuit node, a topology of the circuit model at the input of the active device is suitable for simplification.

4. The method of claim 3, wherein the method is repeated for a plurality of active devices of the circuit model.

5. The method of claim 3, further comprising the step of simplifying internal nodes of the circuit model.

6. The method of claim 5, wherein the step of simplifying internal nodes of the circuit model is performed prior to the step of identifying an active device having an input coupled to a first circuit node.

7. The method of claim 1, further comprising the step of simplifying internal nodes of the circuit model.

8. The method of claim 7, wherein the step of simplifying internal nodes of the circuit model is performed prior to the step of identifying an active device having an input coupled to a first circuit node.

9. The method of claim 8, wherein the step of simplifying internal nodes of the circuit model is performed according to the method of Sheehan.

10. A computer program product comprising a machine readable media having recorded thereon machine readable instructions comprising instructions for execution of the steps:

identifying an active device having an input coupled to a first circuit node coupled to a resistance, where the resistance model is coupled to a second circuit node of the circuit model;

calculating an input capacitance of the active device;

computing a time constant of the resistance and a total capacitance of the circuit node, where the total capacitance of the circuit node includes the input capacitance of the active device;

comparing the time constant to a first threshold; and

if the time constant is less than the threshold, removing the resistance from the circuit model and coupling the input of the active device to the second circuit node.

11. The computer program product of claim 10, wherein the instructions further comprise instructions for iterating the steps of identifying, calculating, computing, comparing, and removing for a plurality of active devices of the circuit model.

12. The computer program product of claim 10, wherein the instructions further comprise instructions for iterating at an input of the active device if the time constant was less than a second threshold and, after removing the resistor from the circuit model and coupling the input of the active device to the second circuit node, a topology of the circuit model at the input of the active device is suitable for simplification.

13. The computer program product of claim 12, wherein the instructions further comprise instructions for iterating the steps of identifying, calculating, computing, comparing, and removing, for a plurality of active devices of the circuit model.

14. The computer program product of claim 12, further comprising machine readable code for simplifying internal nodes of the circuit model.

15. The computer program product of claim 14, wherein the second threshold is equal to the first threshold.

16. The computer program product of claim 15, wherein the second threshold is less than the first threshold.

17. The computer program product of claim 10, further comprising machine readable instructions for simplifying internal nodes of the circuit model.

18. The computer program product of claim 17, wherein simplifying internal nodes of the circuit model is performed prior to identifying an active device having an input coupled to a first circuit node.

19. Apparatus for simplifying a circuit model, the circuit model comprising a plurality of interconnected active device models, resistance models, and capacitance models, comprising:

means for identifying an active device model having an input coupled to a first circuit node coupled to a resistance model, where the resistance model is coupled to a second circuit node of the circuit model;

means for calculating an input capacitance of the active device model;

means for computing a time constant of the resistance model and a total capacitance of the circuit node, where the total capacitance of the circuit node includes the input capacitance of the active device model;

means for comparing the time constant to a threshold; and

if the time constant is less than the threshold, removing the resistance model from the circuit model and altering the circuit model to couple the input of the active device model to the second circuit node.

20. Apparatus for simplifying a circuit model comprising digital computing apparatus having memory, the memory having recorded therein machine-readable instructions for performing steps comprising:

reading a circuit model comprising a plurality of interconnected active device models, resistance models, and capacitance models,

identifying an active device model of the circuit model having an input coupled to a first circuit node coupled to a resistance model, where the resistance model is coupled to a second circuit node of the circuit model;

calculating an input capacitance of the active device;

computing a time constant of the first circuit node from a resistance of the resistance model and a total capacitance of the first circuit node, where the total capacitance of the first circuit node includes the input capacitance of the active device;

comparing the time constant to a threshold, and, if the time constant is less than the threshold, removing the resistance from the circuit model and coupling the input of the active device to the second circuit node; and

repeating the steps of identifying, calculating, computing, and comparing for a plurality of active devices of the circuit model.