Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials

• US 6,673,667 B2
• Filed: 08/15/2001
• Issued: 01/06/2004
• Est. Priority Date: 08/15/2001
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Cornett, Kenneth D., Gorrell, Jonathan F.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/929,021
• Publication Number:
  US 20030036224A1
• Time in Patent Office: 874 Days
• Field of Search: 438/97, 438/77, 438/240, 438/718, 438/970, 438/312, 438/191
• US Class Current: 438/240
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV

Abstract

A method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.

Claims

1. A method for manufacturing a semiconductor apparatus;

the semiconductor apparatus including a substantially integral monolithic semiconductor component including a plurality of materials presenting a plurality of substantially coplanar lands;

the method comprising the steps of;

(a) providing a monocrystalline silicon substrate;

said substrate presenting at least one first land of said plurality of lands;

said monocrystalline silicon being a first material of said plurality of materials;

(b) trenching said substrate from a first side of said substrate to effect at least one cavity in said substrate;

said at least one cavity being appropriately dimensioned to receive at least one semiconductor piece in a finished orientation;

said finished orientation presenting at least one second land of said plurality of lands generally coplanar with said at least one first land;

(c) growing a monocrystalline perovskite oxide on said first side of said substrate to establish an accommodating layer at said first side of said substrate and within said at least one cavity;

said monocrystalline perovskite oxide being a second material of said plurality of materials;

(d) forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between said accommodating layer and said monocrystalline silicon substrate;

(e) growing a template for said at least one semiconductor piece on said oxide to establish a process piece;

said at least one semiconductor piece being at least a portion of the semiconductor apparatus;

(f) growing said at least one semiconductor piece on said process piece;

said at least one semiconductor piece being constructed of a monocrystalline compound semiconductor material;

said monocrystalline compound semiconductor material being a third material of said plurality of materials;

(g) selectively removing predetermined portions of said at least one semiconductor piece and said accommodating layer to establish said at least one semiconductor piece in said finished orientation;

(h) depositing a cap layer on said substantially integral monolithic semiconductor component; and

(i) selectively removing said cap layer to establish a substantially planar face;

said planar face being displaced from said plurality of lands by a predetermined distance.

2. A method for manufacturing a semiconductor apparatus as recited in claim 1, wherein the apparatus is configured for further working using optical manufacturing equipment;

said optical manufacturing equipment having a depth of focus; and

wherein said predetermined distance is less than or equal with said depth of focus.

3. A method for manufacturing a semiconductor apparatus as recited in claim 1, further comprising repeating at least one of the steps (b) through (g) until said substantially integral monolithic semiconductor apparatus is completed.

4. A method for manufacturing a semiconductor apparatus as recited in claim 1, further comprising annealing after said step of growing said at least one semiconductor piece.

5. A method for manufacturing a semiconductor apparatus as recited in claim 1, further comprising annealing after said step of growing said at least one semiconductor piece is started.

7. A method for manufacturing a semiconductor apparatus as recited in claim 5, wherein the apparatus is configured for further working using optical manufacturing equipment;

said optical manufacturing equipment having a depth of focus; and

wherein said predetermined distance is less than or equal with said depth of focus.

8. A method for manufacturing a semiconductor apparatus as recited in claim 5, further comprising repeating at least one of the steps (b) through (g) until said substantially integral monolithic semiconductor apparatus is completed.

9. A method for manufacturing a semiconductor apparatus as recited in claim 5, further comprising annealing after said step of growing said at least one semiconductor piece.

10. A method for manufacturing a semiconductor apparatus as recited in claim 5, further comprising annealing after said step of growing said at least one semiconductor piece has been started.

6. A method for manufacturing a substantially integral monolithic semiconductor apparatus, the method comprising the steps of:

(a) providing a monocrystalline silicon substrate;

said substrate presenting at least one first land of a plurality of lands;

(b) trenching said substrate from a first side of said substrate to effect at least one cavity in said substrate;

said at least one cavity being appropriately dimensioned to receive at least one semiconductor piece in a finished orientation;

said finished orientation presenting at least one second land of said plurality of lands generally coplanar with said at least one first land;

(c) growing a monocrystalline perovskite oxide on said first side of said substrate to establish an accommodating layer at said first side of said substrate and within said at least one cavity;

(d) forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between said accommodating layer and said monocrystalline silicon substrate;

(e) growing a template for said at least one semiconductor piece on said oxide to establish a process piece;

said at least one semiconductor piece being at least a portion of the semiconductor apparatus;

(f) growing said at least one semiconductor piece on said process piece;

said at least one semiconductor piece being constructed of a monocrystalline compound semiconductor material;

(g) selectively removing predetermined portions of said at least one semiconductor piece and said accommodating layer to establish said at least one semiconductor piece in said finished orientation;

(h) depositing a cap layer on said substantially integral monolithic semiconductor component; and

(i) selectively removing said cap layer to establish a substantially planar face;

said planar face being displaced from said plurality of lands by the predetermined distance.