Process for forming MOS-gated power device having segmented trench and extended doping zone

• US 6,673,681 B2
• Filed: 06/19/2002
• Issued: 01/06/2004
• Est. Priority Date: 05/19/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher B., Grebs, Thomas E., Ridley, Rodney S., Cumbo, Joseph L.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US10/174,641
• Publication Number:
  US 20020175412A1
• Time in Patent Office: 566 Days
• Field of Search: 438/259, 438/270, 257/328, 257/329, 257/330
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.

Claims

1. A process for forming a trench MOS-gated device, said process comprising:

providing a substrate having an upper surface and comprising doped monocrystalline semiconductor material of a first conduction type;

forming a trench in an upper layer of said substrate, said trench having a floor and sidewalls, said trench further having a width and extending to a depth substantially corresponding to a width and a depth of the upper segment of an extended trench comprising an upper segment and a bottom segment;

forming a conformal masking oxide layer on said substrate upper layer and on said trench floor and sidewalls;

anisotropically etching said conformal masking oxide layer, thereby removing said masking oxide from said trench floor and forming an opening to substrate semiconductor material underlying said floor;

etching said semiconductor material underlying said trench floor, thereby forming said bottom segment of said extended trench, said bottom segment having a lesser width relative to a greater width of said trench upper segment and extending to a depth corresponding to the total depth of said extended trench;

removing remainder of conformal masking oxide layer from said substrate upper layer and from said trench sidewalls;

substantially filling said extended trench with a dielectric material;

selectively implanting and diffusing a dopant of a second opposite conduction type into said upper layer on one side of said extended trench, thereby forming an extended zone extending from said substrate upper surface into said upper layer;

selectively removing said dielectric material from said upper segment of said extended trench, leaving said bottom segment of said extended trench substantially filled with said dielectric material;

forming floor and sidewalls comprising dielectric material in said upper segment of said extended trench and substantially filling said upper segment with a conductive material, thereby forming a gate region in said upper segment of said extended trench;

forming a doped well region of said second conduction type in said upper layer on the side of said extended trench opposite said extended zone;

forming a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type in said well region at said upper surface;

forming an interlevel dielectric layer on said upper surface overlying said gate and source regions; and

forming a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone.

2. The process of claim 1 further comprising:

forming a doped drain zone of said first conduction type extending through said upper layer and into said substrate beneath said well region and said extended zone.

3. The process of claim 1 wherein said widths of said trench upper segment and said trench bottom segment are in a ratio of about 1.2:

1 to about 12;

1.

4. The process of claim 1 wherein said trench upper segment and said extended trench each extend to a selected depth, said depths of said upper segment and said extended trench being in a ratio, relative to one another, of about 1:

2 to about 1;

8.

5. The process of claim 1 wherein said upper layer is an epitaxial layer.

6. The process of claim 1 wherein said substrate comprises monocrystalline silicon.

7. The process of claim 1 wherein said dielectric material comprises silicon dioxide.

8. The process of claim 1 wherein said conductive material in said trench comprises doped polysilicon.

9. The process of claim 1 wherein said first conduction type is N and said second conduction type is P.

10. The process of claim 1 further comprising:

forming a plurality of extended trenches in said substrate.

11. The process of claim 10 wherein said plurality of extended trenches have an open-cell stripe technology.

12. The process of claim 10 wherein said plurality of extended trenches have a closed-cell cellular topology.

13. The process of claim 1 wherein said device is selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor.