Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers

• US 6,673,698 B1
• Filed: 01/19/2002
• Issued: 01/06/2004
• Est. Priority Date: 01/19/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US10/054,001
• Time in Patent Office: 717 Days
• Field of Search: 438/22, 438/26, 438/48, 438/54, 438/55, 438/57, 438/64, 438/100, 438/101, 438/106, 438/107, 438/455, 438/460, 438/597, 438/584, 438/618, 438/622, 438/758, 438/33, 438/68, 438/108, 438/110, 438/113, 438/114, 438/458, 438/459, 438/462, 438/464, 438/612, 438/613, 438/614, 438/623, 438/778, 438/780, 297/29, 297/38, 297/39, 297/40, 297/62, 228/179.1, 228/180.21, 228/180.22, 257/787, 257/788, 257/700, 257/701, 257/702, 257/703, 257/723, 257/758, 257/724, 257/759, 257/778, 257/779, 257/792
• US Class Current: 438/459
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

Claims

1. A method of fabricating the thin film semiconductor die package structure comprising:

providing a metal substrate;

forming a glass layer with cavities for mounting semiconductor dies on said metal substrate;

sequentially forming polymer insulating layers and metal interconnect layers;

forming a layer of solder; and

reflowing the solder to form solder bumps.

2. A method of fabricating a thin film semiconductor die package structure comprising:

providing a glass substrate with semiconductor dies mounted on the active surface;

filling polymer or epoxy between and over the backside of said semiconductor dies, to obtain a planarized surface;

grinding said backside of said semiconductor dies, to a desired thickness of said semiconductor dies and said polymer or epoxy to obtain a planarized surface;

mounting a second glass substrate on the backside of the semiconductor dies;

grinding the first glass substrate to a desired glass thickness;

etching holes in said first glass substrate to expose said semiconductor dies;

sequentially forming polymer insulating layers and metal interconnect layers over said first glass substrate;

depositing a layer of solder; and

reflowing the solder to form solder bumps.

3. The method of claim 2 wherein said desired thickness of said semiconductor dies is between about 2 and 500 um.

4. The method of claim 2 wherein said desired glass thickness is between about 2 and 150 um.

5. The method of claim 2 further comprising dicing said thin film semiconductor die package structure into single chip semiconductor packages.

6. The method of claim 2 further comprising dicing said thin film semiconductor die package structure into multi-chip semiconductor packages.

7. The method of claim 6 wherein said semiconductor dies mounted within said multi-chip semiconductor packages comprise the same type of integrated circuit chips.

8. The method of claim 6 wherein said semiconductor dies mounted within said multi-chip semiconductor packages comprise different types of integrated circuit chips.

9. The method of claim 2 wherein solder bumps are connected to said interconnect metal and incorporated as interconnects to the next level of assembly.

10. The method of claim 2 wherein connector pins are connected to said interconnect metal and for assembly to the next level of packaging.

11. The method of claim 2 wherein said one or more layers of interconnect metal and said one or more insulating layers comprise an interconnect system, and further comprising incorporating one or more devices within said interconnect system.

12. The method of claim 11 wherein said one or more devices are selected from the group comprising inductors, resistors, capacitors, waveguides, filters and MEMS devices.

13. The method of claim 2 further comprising using said one or more layers of interconnect metal for interconnections between one or more points of electrical contact on each of said semiconductor dies.

14. A method of fabricating a thin film semiconductor die package structure comprising:

providing a glass substrate with semiconductor dies mounted on the active surface;

filling polymer or epoxy between and over the backside of said semiconductor dies,

grinding said backside of said semiconductor dies, to a desired thickness of said semiconductor dies and said polymer or epoxy to obtain a planarized surface;

mounting a second glass substrate on the backside of the semiconductor dies;

removing said first glass substrate;

sequentially forming polymer insulating layers and metal interconnect layers over said semiconductor dies;

depositing a layer of solder; and

reflowing the solder to form solder bumps.

15. The method of claim 14 further comprising using said one or more layers of interconnect metal for interconnections between one or more points of electrical contact on each of said semiconductor dies.