Control of the deposition temperature to reduce the via and contact resistance of Ti and TiN deposited using ionized PVD techniques

• US 6,673,716 B1
• Filed: 01/30/2002
• Issued: 01/06/2004
• Est. Priority Date: 01/30/2001
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Danek, Michal, Tkach, George, Woitge, Michael, DʼCouto, Gerard C.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Pham, Thanhha
• Application Number:
  US10/060,725
• Time in Patent Office: 706 Days
• Field of Search: 438/622, 438/625, 438/627, 438/628, 438/629, 438/642, 438/643, 438/644, 438/648, 438/652-654, 438/656, 438/679, 438/685, 204/192.1, 204/192.11, 204/192.12, 204/192.17, 204/192.15, 204/192.22, 204/192.38, 204/298.01, 204/298.02, 204/298.04, 204/298.09, 204/298.12, 204/298.13, 204/298.15, 204/298.16, 204/298.17, 204/298.18, 204/298.21
• US Class Current: 438/656
• CPC Class Codes: C23C 14/0641 Nitrides C23C14/0617 takes precedence
• CPC Class Codes: C23C 14/185 by cathodic sputtering
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric

Abstract

A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination with controlling the deposition temperatures by integrating cooling steps into the Ti/TiN deposition processes to modulate the via and contact resistance. The Ti and TiN layers are deposited within a single deposition chamber, without the use of a collimator or a shutter.

Claims

1. A method of forming a Ti layer and a TiN layer on an integrated circuit substrate in a single PVD deposition chamber without using either a collimator or a shutter, comprising the steps:

(a) providing a hollow cathode target containing titanium, said hollow cathode target having a cavity region;

(b) providing a substrate within said hollow cathode target, said substrate attached to an electrostatic chuck;

(c) sputtering Ti from said target to form a layer containing Ti on said substrate;

(d) sputtering Ti from said target and simultaneously flowing a nitrogen-containing gas into said deposition chamber to form a layer containing TiN on said substrate; and

(e) controlling the temperature of said substrate prior to deposition of at least one of said layer containing Ti on said substrate of step (c) or said layer containing TiN on said substrate of step (d), wherein step (e) is performed by cooling the substrate by time delay.

2. The method of claim 1 wherein step (e) is performed by applying a temperature controlled electrostatic chuck.

4. The method of claim 1 wherein steps (c) and (e) are performed by applying a temperature controlled electrostatic chuck to said substrate.

3. A method of forming a Ti layer and a TiN layer on an integrated circuit substrate in a single PVD deposition chamber without using either a collimator or a shutter, comprising the steps:

(a) providing a hollow cathode target containing titanium, said hollow cathode target having a cavity region;

(b) providing a substrate within said hollow cathode target, said substrate attached to an electrostatic chuck;

(c) controlling the temperature of said substrate prior to deposition a layer containing Ti on said substrate;

(d) sputtering Ti from said target to form said layer containing Ti on said substrate;

(e) controlling the temperature of said substrate prior to deposition a layer containing TiN on said substrate; and

(f) sputtering Ti from said target and simultaneously flowing a nitrogen-containing gas into said deposition chamber to form said layer containing TiN on said substrates, wherein steps (c) and (e) are performed by cooling the substrate by time delay.

5. The method of claim 3 wherein for the deposition of the Ti layer, said substrate is allowed to cool for a range from about 20 seconds to about 120 seconds.

6. The method of claim 3 wherein for the deposition of the TiN layer, said substrate is allowed to cool for a range from about 20 seconds to about 120 seconds.

7. The method of claim 3 wherein step (b) comprises providing a semiconductor wafer having at least one via formed thereon.

8. The method of claim 3, characterized in that said single deposition chamber does not contain either a collimator or a shutter.

9. The method of claim 3, further comprising creating a magnetic field, said magnetic field having a magnetic null region located between said cavity region and said substrate.

10. The method of claim 3, further comprising heating said substrate to a temperature in a range from about 25°

C. to 350°

C.

11. The method of claim 3, further comprising applying a negative volt in a range from about −

400 to about −

500 volts to said hollow cathode target.

12. The method of claim 3, further comprising applying an amount of power in a range from about 20 to about 36 kilowatts to said hollow cathode target.

13. The method of claim 3, further comprising applying a current not exceeding 1.0 amps to an electromagnetic coil.

14. The method of claim 3, wherein said hollow cathode target and said substrate are separated by a source-to-substrate spacing from about 86 mm to about 106 mm.

15. The method of claim 14, wherein said source-to-substrate spacing is the same during the depositions of said layer containing Ti on said substrate and said layer containing TiN on said substrate.

16. The method of claim 14, wherein said source-to-substrate spacing differs during the depositions of said layer containing Ti on said substrate and said layer containing TiN on said substrate.

17. The method of claim 3, wherein said Ti layer has a thickness in a range from about 10 nm to about 70 nm, while said TiN layer has a thickness in a range from about 10 nm to about 100 nm.

18. A method of forming a Ti layer and a TiN layer on an integrated circuit substrate in a single PVD deposition chamber without using either a collimator or a shutter, comprising the steps:

(a) providing a hollow cathode target containing titanium, said hollow cathode target having a cavity region;

(b) providing a substrate within said hollow cathode target, said substrate attached to an electrostatic chuck;

(c) controlling the temperature of said substrate prior to deposition a layer containing Ti on said substrate by applying a temperature controlled electrostatic chuck to said substrate in addition to cooling said substrate by time delay;

(d) sputtering Ti from said target to form said layer containing Ti on said substrate;

(e) controlling the temperature of said substrate prior to deposition a layer containing TiN on said substrate by applying a temperature controlled electrostatic chuck to said substrate in addition to cooling said substrate by time delay; and

(f) sputtering Ti from said target and simultaneously flowing a nitrogen-containing gas into said deposition chamber to form said layer containing TiN on said substrate.