Semiconductor device and its manufacturing method

• US 6,674,137 B2
• Filed: 11/29/2001
• Issued: 01/06/2004
• Est. Priority Date: 12/01/2000
• Status: Expired due to Term

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: NEC Corporation, NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Nissa, Mitsuo
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): MANDALA, VICTOR A
• Application Number:
  US09/997,593
• Publication Number:
  US 20020135002A1
• Time in Patent Office: 768 Days
• Field of Search: 257/336, 257/344, 257/288, 257/368, 257/382, 257/384, 257/401, 257/412, 257/768, 257/413, 257/390, 257/296, 257/408, 438/386, 438/399, 438/585, 438/592
• US Class Current: 257/408
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate electrode (6) and a side wall insulating film (8) may be formed on the sides of a gate electrode (6) and mask insulating film (7). A low density impurity region (3) may be formed with a gate electrode (6) and side surface insulating film (9) as a mask. A higher density impurity region (4) may be formed with a gate electrode (6) and side wall insulating film (8) as a mask. A contact plug (10) may be formed between side wall insulating films (8) that contacts a higher density impurity region (4). A gate electrode (6) may have a reverse tapered shape when viewed in cross section. A lower layer (6a) may have a reverse tapered shape and/or a side surface insulating film (9) may have a greater thickness on sides of a higher layer (6b) than on a lower layer (6a).

Claims

1. A semiconductor device, comprising:

at least one gate electrode formed over a semiconductor substrate having at least a portion with a reverse tapered shape when viewed in cross section;

a mask insulating film formed on a top surface of the at least one gate electrode;

a side surface insulating film formed on a side surface of the at least one gate electrode;

a side wall insulating film formed on a side surface of the mask insulating film and the at least one gate electrode;

a first impurity region formed in the semiconductor substrate with the at least one gate electrode and the side surface insulating film as a mask, and without the side wall insulating film as a mask; and

a second impurity region formed in the semiconductor substrate with at least the side wall insulating film as a mask, the second impurity region having a higher impurity concentration than the first impurity region.

2. The semiconductor device of claim 1, wherein:

the gate electrode has a laminated structure that includes at least a lower layer and a higher layer, at least the lower layer having a reverse tapered shape when viewed in cross section.

3. The semiconductor device of claim 2, wherein:

the lower layer comprises polysilicon.

4. The semiconductor device of claim 2, wherein:

the higher layer comprises a silicide.

5. The semiconductor device of claim 2, wherein:

the side surface insulating film is thicker on a side of the higher layer than on a side of the lower layer.

6. The semiconductor device of claim 5, wherein:

a line connecting an outer edge of the side surface insulating film on the side of the higher layer to an outer edge of the side surface insulating film on the lower layer has an inclination angle of no more than 15°

with respect to a line normal to the substrate, when the gate electrode is viewed in cross section.

7. The semiconductor device of claim 6, wherein:

the inclination angle is about 7°

.

8. The semiconductor device of claim 1, wherein:

the side surface insulating film is a gate electrode oxide.

9. The semiconductor device of claim 8, wherein:

the side surface insulating film is oxidized in an atmosphere comprising oxygen and within a temperature range of about 1000°

C. to 1100°

C.

10. The semiconductor device of claim 1, wherein:

the gate electrode has a laminated structure that includes at least a lower layer comprising polysilicon and at least an upper layer comprising silicon oxide;

the mask insulating film comprises silicon oxide; and

the side wall insulating film comprises silicon nitride.

11. The semiconductor device of claim 1, further including:

a contact plug connected to the second impurity region and adjacent to the side wall insulating film.

12. The semiconductor device of claim 1, wherein:

a plurality of gate electrodes are separated from one another by a predetermined pitch; and

an interval in the substrate between the end of each gate electrode and an adjacent second impurity region that is greater than a corresponding interval for a gate electrode that does not have a reverse tapered shape.