Recording clock generation circuit

• US 6,674,330 B2
• Filed: 08/08/2002
• Issued: 01/06/2004
• Est. Priority Date: 10/10/2001
• Status: Expired due to Term

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Murata, Yutaka, Ochi, Takahiro, Bokui, Takahiro, Miyada, Yoshinori
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US10/215,159
• Publication Number:
  US 20030067356A1
• Time in Patent Office: 516 Days
• Field of Search: 331/10, 331/11, 331/14, 331/17, 331/25, 331/DIG.2, 327/146, 327/147, 327/155, 327/156, 375/376, 375/375
• US Class Current: 331/11
• CPC Class Codes: G11B 20/10222 clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation dedicated sync patterns in the modulation code G11B20/1403
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: G11B 20/22 for reducing distortions
• CPC Class Codes: G11B 7/0053 Reproducing non-user data, e.g. wobbled address, prepits, BCA
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A recording clock generation circuit includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.

Claims

1. A recording clock generation circuit, comprising:

a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal;

a first filter for smoothing an output from the first phase comparator;

a VCO circuit for oscillating in accordance with the output smoothed by the first filter;

a frequency divider for dividing a frequency of an output from the VCO circuit;

a phase adjusting circuit for adjusting a phase of an output from the frequency divider and providing the PLL internal signal based thereon; and

a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.

2. A recording clock generation circuit according to claim 1, further comprising a second filter, provided between the phase adjusting circuit and the second phase comparator, for filtering the phase difference detected by the second phase comparator.