Multi-instruction stream processor

• US 6,674,536 B2
• Filed: 02/18/1998
• Issued: 01/06/2004
• Est. Priority Date: 04/30/1997
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Amies, Christopher, Gibson, Ian, Long, Timothy Merrick
• Primary Examiner(s): Garcia, Gabriel
• Assistant Examiner(s): Tran, Douglas
• Application Number:
  US09/025,768
• Publication Number:
  US 20020057446A1
• Time in Patent Office: 2,148 Days
• Field of Search: 395/109, 395/114, 395/115, 358/1.15, 358/1.9, 358/1.6, 358/1.13, 345/502-506, 712/34
• US Class Current: 358/1.15
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering

Abstract

The present invention discloses apparatus for, and a method of, rendering image data prior to outputting of the resulting image. A graphics co-processor (224) is utilized together with a host CPU (202), the former having a plurality of data calculation streams (241, 242, 243) arranged in parallel fashion. Only one of the data calculation streams (241, 242, 243) is operated at any one time. Preferably at least one (242) of the data calculation streams is able to be reconfigured.

Claims

1. A method of rendering image data, said method comprising the steps of:

generating a plurality of instruction streams; and

executing instructions one at a time within a graphics co-processor,

wherein the graphics co-processor comprises one or more reconfigurable units for executing the instructions, and

wherein said executing step comprises the sub-steps of;

(a) determining one instruction stream from the plurality of instruction streams in accordance with a priority and one or more predefined priority rules;

(b) fetching an instruction not previously fetched from the determined instruction stream;

(c) decoding the fetched instruction;

(d) reconfiguring the one or more reconfigurable units in accordance with the decoded fetched instruction;

(e) executing the decoded fetched instruction; and

(f) repeating the sub-steps (a) through (e).

2. A method as claimed in claim 1, further comprising the step of normalizing the image data prior to said executing step.

3. A method as claimed in claim 1, wherein the plurality of instruction streams numbers two instruction streams.

4. A method as claimed in claim 1, wherein the plurality of instruction steams numbers three instruction streams.

5. A method as claimed in claim 1, further comprising the step of outputting a resulting image by printing the image on a printer.

6. A method as claimed in claim 1,

wherein the determining sub-step comprises:

determining whether there is any instruction not yet fetched from the plurality of instruction streams that are pending; and

, if so,

determining an instruction stream comprising a pending instruction having a highest priority, and

wherein the fetching sub-step comprises;

fetching the pending instruction having the highest priority.

7. A method as claimed in claim 1, wherein the one or more predefined priority rules include a rule that any one of the instruction steams that is designated as locked will be determined as being an instruction stream from which an instruction is to be fetched irrespective of an availability of instructions in another instruction stream.

8. A method as claimed in claim 1, wherein said method further comprises the steps of:

generating in a host processor the plurality of instruction streams; and

buffering the plurality of instruction streams for access by the graphics co-processor.

9. The method as claimed in claim 1, wherein the one or more predefined priority rules include a rule that an instruction stream designated as having a highest priority will be determined as being an instruction stream from which an instruction is to be fetched.

10. The method as claimed in claim 1, wherein

the plurality of instruction streams numbers two instruction streams, and

the one or more predefined priority rules include a rule that an instruction stream will be determined as being an instruction stream from which an instruction is to be fetched, when its priority is a predetermined priority and a previous instruction last fetched was from another instruction stream.

11. Apparatus adapted for rendering image data, said apparatus comprising:

a graphics co-processor for accessing and executing instructions of a plurality of instruction streams, said graphics co-processor comprising;

one or more reconfigurable units;

a unit for determining one instruction stream from the plurality of instruction streams in accordance with a current priority and one or more predefined priority rules;

a unit for fetching an instruction not previously fetched from the determined instruction stream;

a unit for decoding the fetched instruction; and

a unit for reconfiguring the one or more reconfigurable units in accordance with the decoded instruction,

wherein each reconfigurable unit is adapted to execute the decoded instruction.

12. Apparatus as claimed in claim 11, wherein the plurality of instruction streams numbers two instruction streams.

13. Apparatus as claimed in claim 11, wherein the plurality of instruction streams numbers three instruction streams.

14. An apparatus as claimed in claim 11, further comprising a data normalization unit positioned upstream of the plurality of instruction streams.

15. An apparatus as claimed in claim 11, further comprising a printer to which a resulting image is outputted to be printed.

16. An apparatus as claimed in claim 11, wherein said graphics co-processor further comprises:

a device for determining whether there is any instruction of the plurality of instruction streams pending, and for determining an instruction stream comprising a pending instruction having a highest priority.

17. An apparatus as claimed in claim 16,

wherein the one or more priority rules includes a rule that any one of the instruction streams that is designated as locked will be determined as being an instruction stream from which an instruction is to be fetched irrespective of an availability of instructions in another instruction stream, and

wherein said graphics co-processor further comprises a device for determining any one instruction stream from the plurality of instruction streams that is designated as locked.

18. An apparatus according to claim 11, further comprising:

a host processor for generating the plurality of instruction streams;

a buffer for buffering the plurality of instruction streams generated by said host processor for access by said graphics co-processor.

19. Apparatus adapted for rendering image data, said apparatus comprising:

a host processor for generating a plurality of instruction streams; and

a graphics co-processor for accessing and executing the instructions of the plurality of instruction streams, said graphics co-processor comprising;

one or more reconfigurable units;

a unit for determining one instruction stream from the plurality of instruction streams in accordance with a current priority and one or more predefined priority rules;

a unit for fetching an instruction not previously fetched from the determined instruction stream;

a unit for decoding the fetched instruction; and

a unit for reconfiguring the one or more reconfigurable unit in accordance with the decoded instruction,

wherein each reconfigurable unit is adapted to execute the decoded instruction.

20. An apparatus as claimed in claim 19, wherein the plurality of instruction streams numbers two instruction streams.

21. An apparatus as claimed in claim 19, wherein the plurality of instruction streams numbers three instruction streams.

22. An apparatus as claimed in claim 19, further comprising a data normalization unit positioned upstream of the plurality of instruction streams.

23. An apparatus as claimed in claim 19, further comprising a printer to which a resulting image is outputted to be printed.

24. Apparatus adapted for rendering image data, said apparatus comprising:

a host processor for generating a plurality of streams of instructions; and

a graphics co-processor for accessing and executing instructions of the plurality of instruction streams, wherein said graphics co-processor is adapted to operate in conjunction with said host processor, said graphics co-processor comprising;

one or more reconfigurable units;

a unit for determining one instruction stream from the plurality of instruction streams in accordance with a current priority and one or more predefined priority rules;

a unit for fetching an instruction not previously fetched from the determined instruction stream;

a unit for decoding the fetched instruction; and

a unit for reconfiguring the one or more reconfigurable units in accordance with the decoded instruction,

wherein each reconfigurable unit is adapted to perform image calculations on a stream of image data in accordance with the decoded instruction.