Read circuit on nonvolatile semiconductor memory
First Claim
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1. A read circuit of a nonvolatile semiconductor memory comprising:
- at least one sense amplifier; and
a read control signal generating circuit for supplying a first signal to said at least one sense amplifier, wherein said at least one sense amplifier has a first current path comprised of a first P-channel MOS transistor having a source electrically connected to a first power supply node and a gate applied with said first signal, and a first N-channel MOS transistor connected between a drain of said first P-channel MOS transistor and a memory cell and having a gate applied with a second signal, and said read control signal generating circuit has a second current path comprised of a second P-channel MOS transistor having a gate and a drain connected to the gate of said first P-channel MOS transistor and a source electrically connected to said first power supply node, and a second N-channel MOS transistor connected between the drain of said second P-channel MOS transistor and a reference cell and having a gate applied with a third signal.
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Abstract
An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.
52 Citations
15 Claims
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1. A read circuit of a nonvolatile semiconductor memory comprising:
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at least one sense amplifier; and
a read control signal generating circuit for supplying a first signal to said at least one sense amplifier, wherein said at least one sense amplifier has a first current path comprised of a first P-channel MOS transistor having a source electrically connected to a first power supply node and a gate applied with said first signal, and a first N-channel MOS transistor connected between a drain of said first P-channel MOS transistor and a memory cell and having a gate applied with a second signal, and said read control signal generating circuit has a second current path comprised of a second P-channel MOS transistor having a gate and a drain connected to the gate of said first P-channel MOS transistor and a source electrically connected to said first power supply node, and a second N-channel MOS transistor connected between the drain of said second P-channel MOS transistor and a reference cell and having a gate applied with a third signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
for monitoring a threshold voltage of said memory cell having a positive threshold voltage, the potential at the control gate electrode of said reference cell is fixed to the value for the normal read operation, and a potential at the control gate electrode of said memory cell is varied to detect the threshold voltage of said memory cell.
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8. The read circuit according to claim 1, wherein said at least one sense amplifier includes an inverter which functions as a sense circuit;
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said inverter is comprised of a third P-channel MOS transistor having a gate applied with a fourth signal, a source connected to said first power supply node, and a drain connected to an output node; and
a third N-channel MOS transistor having a gate connected to a connection node between said first P-channel MOS transistor and said first N-channel MOS transistor, a source connected to a second power supply node, and a drain connected to said output node; and
said inverter discriminates data in said memory cell by detecting a change in a potential at said connection node.
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9. The read circuit according to claim 8, wherein said connection node is precharged to a potential lower than a threshold voltage of said inverter before a sense operation.
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10. The read circuit according to claim 1, wherein said read control signal generating circuit includes a precharge circuit, said precharge circuit precharging a first connection node between said second P-channel MOS transistor and said second N-channel MOS transistor, and a second connection node between said second N-channel MOS transistor and said reference cell, respectively, for a period other than a first period in which a cell current is flowing into said reference cell.
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11. The read circuit according to claim 10, wherein a potential at said first connection node in a second period is set to a value identical to or lower than the potential at said first connection node in said first period, and a potential at said second connection node in said second period is set to a value identical to or lower than the potential at said second connection node in said first period.
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12. The read circuit according to claim 1, wherein said at least one sense amplifier includes an N-channel MOS transistor which is connected in parallel with said first N-channel MOS transistor, and transitions to an ON state when a bit line is precharged.
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13. The read circuit according to claim 1, wherein a potential on a bit line is reset before said bit line is precharged.
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14. The read circuit according to claim 13, wherein a precharge period is provided for said bit line subsequent to a reset period for said bit line, said bit line being selected in the reset period of said bit line.
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15. The read circuit according to claim 13, wherein the gate of said first N-channel MOS transistor is connected to said first power supply node when said bit line is precharged.
Specification