Memory device tester and method for testing reduced power states

• US 6,674,677 B2
• Filed: 06/12/2002
• Issued: 01/06/2004
• Est. Priority Date: 09/02/1999
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Hyslop, Adin E., Harrington, Matthew R., Huynh, Van C.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/166,887
• Publication Number:
  US 20020149981A1
• Time in Patent Office: 573 Days
• Field of Search: 365/201, 365/227, 365/228, 365/229, 365/230.06, 714/21, 714/22
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/024 in decoders
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Claims

1. A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:

issuing a first command to the memory device to put the memory device in the reduced power state, wherein the command is decoded by one of a row decoder or a column decoder of the memory device;

issuing a second command to the memory device, wherein the second command is directed to the column decoder; and

comparing a data value returned by the memory device against an expected value to verify that the column decoder did not decode the second command.

2. The method of claim 1 wherein the column decoder is disabled in the reduced power state.

3. The method of claim 1 wherein the memory device is a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the first command is issued on the row control bus to be decoded by the row decoder.

4. The method of claim 1 wherein the memory device is a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the first command is issued on the column control bus to be decoded by the column decoder.

5. The method of claim 1 wherein:

the memory device is a Direct Rambus Dynamic Random Access Memory coupled to a row control bus and a column control bus;

the reduced power state is a standby (STBY) state; and

the first command is a relax (RLX) command issued on the row control bus to be decoded by the row decoder.

6. The method of claim 1, wherein the method is performed in the order presented.

7. A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:

issuing a relax command (RLX) to the memory device to put the memory device in the reduced power state, wherein the relax command is decoded by a row decoder of the memory device;

issuing a second command to the memory device; and

comparing a data value returned by the memory device against an expected value to verify that the memory device did not decode the second command.

8. The method of claim 7 wherein the second command is directed to a column decoder within the memory device.

9. The method of claim 7 wherein the memory device comprises a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the first command is issued on the row control bus to be decoded by the row decoder.

10. A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:

issuing a command to the memory device to put the memory device in the reduced power state, wherein the command is decoded by a column decoder of the memory device;

issuing a second command to the memory device; and

comparing a data value returned by the memory device against an expected value to verify that the memory device did not decode the second command.

11. The method of claim 10 wherein the memory device comprises a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the first command is issued on the column control bus to be decoded by the column decoder.

12. The method of claim 10 wherein the second command is directed to a column decoder within the memory device.

13. A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:

issuing a first command to the memory device to put the memory device in the reduced power state, wherein the command is decoded by one of a row decoder or a column decoder of the memory device;

issuing a second command to the memory device, wherein the second command is directed to the column decoder;

comparing a first data value returned by the memory device against an expected value to verify that the column decoder did not decode the second command;

issuing a third command to the memory device to put the memory device in an attention state;

issuing a fourth command to the memory device, wherein the fourth command is directed to the column decoder; and

comparing a second data value returned by the memory device against an expected value to verify that the column decoder decoded the fourth command.

14. The method of claim 13 wherein the second command comprises a calibrate (CAL) command.

15. The method of claim 13 wherein the memory device comprises a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the first command is issued on the column control bus to be decoded by the column decoder.

16. The method of claim 13 wherein the memory device comprises a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the third command is issued on the row control bus to be decoded by the row decoder.

17. The method of claim 16 wherein the third command comprises a No Row Operation (NoRop) command.

18. A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:

issuing a relax command (RLX) to the memory device to put the memory device in the reduced power state, wherein the relax command is decoded by a row decoder of the memory device;

issuing a second command to the memory device;

comparing a first data value returned by the memory device against an expected value to verify that the column decoder did not decode the second command;

issuing a third command to the memory device to put the memory device in an attention state;

issuing a fourth command to the memory device, wherein the fourth command is directed to the column decoder; and

comparing a second data value returned by the memory device against an expected value to verify that the column decoder decoded the fourth command.

19. The method of claim 18 wherein the second command comprises a calibrate (CAL) command.

20. The method of claim 18 wherein the memory device comprises a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the first command is issued on the column control bus to be decoded by the column decoder.

21. The method of claim 18 wherein the memory device comprises a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the third command is issued on the row control bus to be decoded by the row decoder.

22. The method of claim 21 wherein the third command comprises a No Row Operation (NoRop) command.

23. A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:

issuing a command to the memory device to put the memory device in the reduced power state, wherein the command is decoded by a column decoder of the memory device;

issuing a second command to the memory device;

comparing a first data value returned by the memory device against an expected value to verify that the column decoder did not decode the second command;

issuing a third command to the memory device to put the memory device in an attention state;

issuing a fourth command to the memory device, wherein the fourth command is directed to the column decoder; and

comparing a second data value returned by the memory device against an expected value to verify that the column decoder decoded the fourth command.

24. The method of claim 23 wherein the second command comprises a calibrate (CAL) command.

25. The method of claim 23 wherein the memory device comprises a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the first command is issued on the column control bus to be decoded by the column decoder.

26. The method of claim 23 wherein the memory device comprises a Direct Rambus Dynamic Random Access Memory which is coupled to a row control bus and a column control bus, and wherein the third command is issued on the row control bus to be decoded by the row decoder.

27. The method of claim 26 wherein the third command comprises a No Row Operation (NoRop) command.

28. A method of testing for the proper operation of a reduced power state in a memory device having rows and columns of memory cells, the method comprising:

issuing a first command to the memory device to put the memory device in the reduced power state, wherein the command is decoded by one of a row decoder or a column decoder of the memory device;

issuing a first calibrate command to the memory device;

issuing a second command to the memory device to cause the memory device to leave the reduced power state;

issuing a second calibrate command to the memory device; and

comparing a data value returned by the memory device against an expected value.

29. The method of claim 28 wherein the column decoder is disabled in the reduced power state.

30. The method of claim 28 wherein:

the memory device is a Direct Rambus Dynamic Random Access Memory coupled to a row control bus and a column control bus;

the reduced power state is a standby (STBY) state; and

the first command is a relax (RLX) command issued on the row control bus to be decoded by the row decoder.