×

Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants

  • US 6,675,265 B2
  • Filed: 06/11/2001
  • Issued: 01/06/2004
  • Est. Priority Date: 06/10/2000
  • Status: Expired due to Fees
First Claim
Patent Images

1. A computer system, comprising:

  • an interconnect;

    a plurality of processor nodes, coupled to the interconnect, each processor node including;

    at least one processor core, each processor core having an associated memory cache for caching memory lines of information;

    an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information; and

    a protocol engine implementing a predefined cache coherence protocol;

    wherein the local memory subsystem is embodied upon a single chip, along with the processor core, the memory cache, the interface and the protocol engine; and

    the computer system further comprises;

    a plurality of input/output nodes, coupled to the interconnect, each input/output node including;

    no processor cores;

    an input/output interface for interfacing to an input/output bus or input/output device;

    a memory cache for caching memory lines of information;

    an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information; and

    a protocol engine implementing the predefined cache coherence protocol;

    wherein the local memory subsystem is embodied upon another single chip, along with the input/output interface, the memory cache, the interface and the protocol engine;

    wherein the protocol engine of each of the processor nodes and the protocol engine of each of the input/output nodes includes logic for sending an initial invalidation request to no more than a first predefined number of the processor nodes and input/output nodes associated with set bits in an identification field of a directory entry associated with a requested memory line of information; and

    wherein the processor nodes and the input/output nodes collectively comprise a plurality of system nodes, each of which includes;

    input logic for receiving a first invalidation request, the invalidation request identifying a memory line of information and including a pattern of bits for identifying a subset of the plurality of system nodes that potentially store cached copies of the identified memory line; and

    processing circuitry, responsive to receipt of the first invalidation request, for determining a next node identified by the pattern of bits in the invalidation request and for sending to the next node, if any, a second invalidation request corresponding to the first invalidation request, and for invalidating a cached copy of the identified memory line, if any, in the particular node of the computer system.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×