Method and apparatus for coordinating memory operations among diversely-located memory components

• US 6,675,272 B2
• Filed: 04/24/2001
• Issued: 01/06/2004
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Ware, Frederick A., Tsern, Ely K., Hampel, Craig E.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US09/841,911
• Publication Number:
  US 20020174311A1
• Time in Patent Office: 987 Days
• Field of Search: 711/157, 711/158, 711/163, 711/167, 711/5, 711/101, 711/170
• US Class Current: 711/167
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

Claims

1. A memory system comprising:

a memory controller component;

a rank of memory components comprising slices; and

conductors coupling the memory controller component to the rank of memory components and coupling the memory controller component to the slices of the rank of memory components, wherein a propagation delay of one of the conductors carrying a signal selected from a group consisting of an address signal, a write data signal, and a read data signal is longer than an amount of time that an element of information represented by the signal is applied to the conductor, wherein the conductors comprise;

a common address bus coupling the memory controller component to each of the slices of the rank in succession; and

separate data buses coupling the memory controller component to each of the slices of the rank.

2. The memory system of claim 1 wherein the common address bus is coupled to a plurality of the slices.

3. The memory system of claim 2 wherein the separate data buses comprise:

a first data bus coupling the memory controller component to a first slice of the slices; and

a second data bus coupling the memory controller component to a second slice of the slices, wherein the first data bus and the second data bus carry different signals independently of each other.

4. A memory system comprising:

a memory controller component;

a rank of memory components comprising slices; and

conductors coupling the memory controller component to the slices of the rank of memory components, wherein the conductors comprise a first data bus coupled to the memory controller component and the first slice and a second data bus coupled to the memory controller component and the second slice, the first data bus being separate from the second data bus, wherein first elements of information relating to the first slice are driven on a first conductor of the conductors coupled to the first slice for a first element time interval from a first time to a second time, wherein second elements of information relating to the second slice are driven on a second conductor of the conductors coupled to the second slice for a second element time interval from a third time to a fourth time, and wherein the memory controller component comprises a logic circuit adapted to allow sampling of the first elements of information and the second elements of information when there exists a difference between the first time and the third time that is greater than a first duration of the first element time interval.

5. The memory system of claim 4 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

6. A memory system comprising:

a memory controller component;

a rank of memory components comprising slices, the slices comprising a first slice and a second slice;

conductors coupling the memory controller component to the slices of the rank of memory components, wherein the conductors comprise a first data bus coupled to the memory controller component and the first slice and a second data bus coupled to the memory controller component and the second slice, the first data bus being separate from the second data bus, wherein first elements of information relating to the first slice are driven on a first conductor of the conductors coupled to the first slice for a first element time interval from a first time to a second time, wherein second elements of information relating to the second slice are driven on a second conductor of the conductors coupled to the second slice for a second element time interval from a third time to a fourth time; and

a logic circuit adapted to allow sampling of the first elements of information and the second elements of information when there exists a difference between the first time and the third time that is greater than a cycle time of a clock circuit of the memory controller component.

7. The memory system of claim 6 wherein the logic circuit is incorporated into the memory controller component.

8. The memory system of claim 6 wherein the logic circuit is incorporated into at least one of the memory components.

9. The memory system of claim 6 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

10. A memory system comprising:

a memory controller component;

a rank of memory components comprising slices, the slices comprising a first slice and a second slice;

a common address bus connecting coupling the memory controller component to the first slice I and the second slice in succession;

a first data bus coupling the memory controller component to the first slice; and

I

a second data bus coupling the memory controller component to the second slice, the first data bus being separate from the second data bus, wherein first elements of information are driven on the first data bus for a first element time interval from a first time to a second time, wherein second elements of information are driven on the second data bus for a second element time interval from a third time to a fourth time, wherein third elements of information are driven on the common address bus for a third element time interval from a fifth time to a sixth time, wherein there is a first access time interval between the fifth time and the first time, wherein fourth elements of information are driven on the common address bus for a fourth element time interval from a seventh time to an eighth time, wherein there is a second access time interval between the seventh time and the third time, and wherein at least one of the memory components of the rank of memory components comprises a logic circuit adapted to allow sampling of the first elements of information and the second elements of information when there exists a difference between the first access time interval and the second access time interval that is greater than a first duration of the first element time interval.

11. The memory system of claim 10 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

12. A memory system comprising:

a memory controller component;

a rank of memory components comprising slices, the slices comprising a first slice and a second slice;

conductors coupling the memory controller component to the slices of the rank of memory components, wherein the conductors comprise a first data bus coupled to the memory controller component and the first slice and a second data bus coupled to the memory controller component and the second slice, the first data bus being separate from the second data bus, wherein first elements of information relating to the first slice are driven on a first conductor of the conductors coupled to the first slice for a first element time interval, the first element time interval associated with a first timing signal event, wherein second elements of information relating to the second slice are driven on a second conductor of the conductors coupled to the second slice for a second element time interval, the second element time interval associated with a second timing signal event; and

a logic circuit adapted to allow sampling of the first elements of information and the second elements of information when there exists a difference between the first timing signal event and the second timing signal event that is greater than a duration selected from a group consisting of the first element time interval and a cycle time of a clock circuit of the memory controller component.

13. The memory system of claim 12 wherein the logic circuit is incorporated into the memory controller component.

14. The memory system of claim 12 wherein the logic circuit is incorporated into at least one of the memory components.

15. The memory system of claim 12 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

16. A memory system comprising:

a memory controller component;

a rank of memory components comprising slices, the slices comprising a first slice and a second slice;

a common address bus coupling the memory controller component to the first slice and the second slice in succession;

a first data bus coupling the memory controller component to the first slice; and

a second data bus coupling the memory controller component to the second slice, wherein first elements of information are driven on the first data bus for a first element time interval, the first element time interval associated with a first timing signal event, wherein second elements of information are driven on the second data bus for a second element time interval, the second element time interval associated with a second timing signal event, wherein third elements of information are driven on the common address bus for a third element time interval, the third element time interval associated with a third timing signal event, wherein there is a first access time interval between the third timing signal event and the first timing signal event, wherein fourth elements of information are driven on the common address bus for a fourth element time interval, the fourth element time interval associated with a fourth timing signal event, wherein there is a second access time interval between the fourth timing signal event and the second timing signal event, and wherein at least one of the memory components of the rank of memory components comprises a logic circuit adapted to allow sampling of the first elements of information and the second elements of information when there exists a difference between the first access time interval and the second access time interval that is greater than a first duration of the first element time interval.

17. The memory system of claim 16 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

18. A memory component adapted to be coupled to a memory controller component as a first slice of a rank of memory components, the rank further comprising a second slice, wherein conductors couple the memory controller component to the first slice and the second slice, the conductors comprising a first data bus coupling the first slice to the memory controller component and a second data bus coupling the second slice to the memory controller component, the first data bus being separate from the second data bus, the memory component comprising:

a logic circuit adapted to cause the memory controller component to allow sampling of first elements of information and second elements of information when there exists a difference between a first time and a third time that is greater than a first duration of a first element time interval, wherein the first elements of information are driven on a first conductor of the conductors coupled to the first slice for the first element time interval from the first time to a second time, wherein the second elements of information relating to the second slice are driven on a second conductor of the conductors coupled to the second slice for a second element time interval from the third time to a fourth time.

19. The memory component of claim 18 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

20. A memory component adapted to be coupled to a memory controller component as a first slice of a rank of memory components, the rank further comprising a second slice, a common address bus coupling the memory controller component to the first slice and the second slice in succession, a first data bus coupling the memory controller component to the first slice, a second data bus coupling the memory controller component to the second slice, the first data bus being separate from the second data bus, the memory component comprising:

a logic circuit adapted to allow sampling of first elements of information and second elements of information when there exists a difference between a first access time interval and a second access time interval that is greater than a first duration of a first element time interval, wherein the first elements of information are driven on the first data bus for the first element time interval from a first time to a second time, wherein the second elements of information are driven on the second data bus for a second element time interval from a third time to a fourth time, wherein third elements of information are driven on the common address bus for a third element time interval from a fifth time t a sixth time, wherein the first access time interval occurs between the fifth time and the first time, wherein fourth elements of information are driven on the common address bus for a fourth element time interval from a seventh time to an eighth time, wherein the second access time interval occurs between the seventh time and the third time.

21. The memory component of claim 20 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

22. A memory component adapted to be coupled to a memory controller component as a first slice of a rank of memory components, the rank further comprising a second slice, wherein conductors couple the memory controller component to the slices of the rank of memory components, the conductors comprising a first data bus coupled to the memory controller component and the first slice and a second data bus coupled to the memory controller component and the second slice, the first data bus being separate from the second data bus, the memory component comprising:

a logic circuit adapted to cause the memory controller component to allow sampling of first elements of information and second elements of information when there exists a difference between a first timing signal event and a second timing signal event that is greater than a first duration of a first element time interval, wherein the first elements of information are driven on a first conductor of the conductors coupled to the first slice for the first element time interval, the first element time interval associated with the first timing signal event, wherein the second elements of information relating to the second slice are driven on a second conductor of the conductors coupled to the second slice for a second element time interval, the second element time interval associated with the second timing signal event.

23. The memory component of claim 22 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

24. A memory component adapted to be coupled to a memory controller component as a first slice of a rank of memory components, the rank of memory components further comprising a second slice, a common address bus coupling the memory controller component to the first slice and the second slice in succession, a first data bus coupling the memory controller component to the first slice, a second data bus coupling the memory controller component to the second slice, the memory component comprising:

a logic circuit adapted to allow sampling of first elements of information and second elements of information when there exists a difference between a first access time interval and a second access time interval that is greater than a first duration of a first element time interval, wherein the first elements of information are driven on the first data bus for the first element time interval, the first element time interval associated with a first timing signal event, wherein the second elements of information are driven on the second data bus for a second element time interval, the second element time interval associated with a second timing signal event, wherein third elements of information are driven on the common address bus for a third element time interval, the third element time interval associated with a third timing signal event, wherein the first access time interval occurs between the third timing signal event and the first timing signal event, wherein fourth elements of information are driven on the common address bus for a fourth element time interval, the fourth element time interval associated with a fourth timing signal event, wherein the second access time interval occurs between the fourth timing signal event and the second timing signal event.

25. The memory component of claim 24 wherein the logic circuit is further adapted to introduce a delay to allow sampling of the first elements of information and the second elements of information.

26. A method for conducting memory operations in a memory system comprising a memory controller component and a rank of memory components comprising slices, the slices comprising a first slice and a second slice, the memory controller component coupled to conductors, the conductors including a common address bus coupling the memory controller component to the first slice and the second slice, a first data bus coupling the memory controller component to the first slice, and a second data bus coupling the memory controller component to the second slice, the first data bus being separate from the second data bus, the method comprising the step of:

providing said memory system;

providing a signal to one of the conductors, the signal selected from a group consisting of an address signal, a write data signal, and a read data signal, wherein the propagation delay of the one of the conductors is longer than an amount of time that an element of information represented by the signal is applied to the conductor; and

using the signal to conduct the memory operations.

27. The method of claim 26 further comprising the step of:

providing a first data signal to the first data bus and a second data signal to the second data bus, the first data signal relating specifically to the first slice and the second data signal relating specifically to the second slice.

28. A method for coordinating memory operations among a first memory component and a second memory component, the method comprising the steps of:

applying a first address signal relating to the first memory component to a common address bus over a first time interval, the common address bus coupled to the first memory component and the second memory component;

applying a second address signal relating to the second memory component to the common address bus over a second time interval, the first time interval being shorter than a propagation delay of the common address bus and the second time interval being shorter than a common address bus propagation delay of the common address bus; and

controlling a first memory operation of the first memory component using a first memory component timing signal, the first memory component timing signal dependent upon a first relationship between the common address bus propagation delay and a first data bus propagation delay of a first data bus coupled to the first memory component; and

controlling a second memory operation of the second memory component using a second memory component timing signal, the second memory component timing signal dependent upon a second relationship between the common address bus propagation delay and a second data bus propagation delay of a second data bus coupled to the second memory component.