PC card controller with advanced power management reset capabilities

• US 6,675,303 B1
• Filed: 09/22/2000
• Issued: 01/06/2004
• Est. Priority Date: 09/29/1999
• Status: Active Grant

• Current Assignee: Maishi Electronic (Shanghai) Limited
• Original Assignee: 2micro International Limited
• Inventors: Lam, James, Huang, Yishao Max, Koilada, Rajesh B., Li, Jeng-Luen Allen
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): CHUNG TRANS, XUONG MY
• Application Number:
  US09/667,644
• Time in Patent Office: 1,201 Days
• Field of Search: 710/300, 710/301, 713/300-340, 713/1
• US Class Current: 713/320
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision

Abstract

A power management PC expansion card controller that includes power on reset circuitry to reset power management enable registers during a reset period, thereby ensuring that the PME registers correctly identify the power management capabilities of the controller. Once the PME registers are reset, an instruction may be provided to change the state of the registers from a default reset state to a state that supports advanced power management capabilities, for example wake-up functions. Additionally, the controller includes blocking circuitry to block conventional reset signals from resetting the power management and proprietary registers if the PME register is instructed to change states, thereby preserving the data contained in the power management and proprietary registers against future reset events. The controller of the present invention supports advanced power management specifications without requiring additional pinout arrangement or reassignment of pin functionality, so that the controller of the present invention can be implemented in current computer system without a the need for retooling or re-layout of system board circuitry and wiring diagrams.

Claims

1. A PC card controller, comprising:

power management event enable (PME) registers, said PME registers being reset to a default state and generating a control signal indicative of said default state, and said PMF registers adapted to receive instruction to change from a default state to a different state and generating a control signal indicative of said different state;

power management registers;

a trigger signal that changes state when power is first applied to said PME registers;

power on reset circuitry receiving said trigger signal and generating a first reset signal to reset said PME registers when said power is first applied to said PME registers, and generating a second reset signal to reset said power management registers when said power is first applied to said power management registers; and

blocking circuitry receiving a conventional reset signal for said power management registers and said control signal and generating said second reset signal, wherein once said control signal indicates a different state, said blocking circuitry preventing said power management registers from being reset by said conventional reset signal.

2. A controller as claimed in claim 1, wherein said default state comprising a state that does not support wake-up functions and said different sate comprising a state that supports wake-up functions.

3. A controller as claimed in claim 1, wherein said power management registers comprise PCI and CardBus power management preserve registers and proprietary registers, and said conventional reset signal comprises a PCI reset signal.

4. A controller as claimed in claim 1 wherein said blocking circuitry comprising an AND gate receiving said conventional reset signal for said power management registers and said control signal and generating said second reset signal.

5. A controller as claimed in claim 1, wherein said instruction being generated by an operating system in communication with said PME registers, wherein said default state being defined as a state where power management events are disabled, and said instruction from said operating system changing the state of said PME registers to enable power management events.

6. A controller as claimed in claim 1, wherein said power on reset circuitry adapted to generate said reset signal before said trigger signal reaches a predetermined threshold power level.

7. A controller as claimed in claim 6, wherein said trigger signal comprises an AUXVCC signal, and said circuitry comprising an RC circuit chosen to generate said first reset signal.

8. A controller as claimed in claim 1, wherein said power on reset circuitry comprising a flip-flop circuit, said trigger signal is a conventional reset signal, and wherein said flip-flop adapted to receive said trigger signal and a signal that changes state only when said power is first applied to said registers and generate said first reset signal.

9. A controller as claimed in claim 8, wherein said trigger signal comprising a PCI reset signal, said PCI reset signal changing states when said power is first applied to said register and thereafter changing states based on external reset commands and wherein once said PCI reset signal changes state twice, said flip-flop circuit being adapted to permanently disable said first reset signal until said signal changes state again when said power is first applied to said system.

10. A controller as claimed in claim 1, wherein said power on reset circuitry adapted to generate said first reset signal and reset said PiM registers only when power is first applied to said registers.

11. A method for resetting one or more registers of a PC card controller, said method comprising the steps of:

choosing a triggering signal that changes power levels when power is first applied to power management event enable (PME) registers;

generating a reset signal based on said triggering signal;

resetting said PME registers using said reset signal;

generating a second reset signal;

resetting power management registers with said second reset signal;

generating a control signal indicative of the reset state of said PME registers;

instructing the reset PME register to change state;

changing the state of said control signal; and

blocking additional resets of said power management registers.

12. A method as claimed in claim 11, further comprising the steps of:

generating a control signal indicative of the reset state of said PME registers; and

ANDing said first control signal and a conventional reset signal and generating said second reset signal.

13. A method as claimed in claim 11, further comprising the steps of:

defining a predetermined threshold voltage level for said trigger signal;

generating said reset signal based on said predetermined threshold voltage level.

14. A method as claimed in claim 11, further comprising the steps of:

choosing a conventional reset signal;

inputting said conventional reset signal and said trigger signal into a flip-flop; and

generating said reset signal until a trigger of said flip-flop changes state twice from an initial state.

15. A CardBus controller, comprising power management event enable (PME) registers;

PCI and CardBus power management registers;

a trigger signal that changes state when power is first applied to said PME registers, PCI and Cardbus registers;

power on reset circuitry receiving said trigger signal and generating a first reset signal to reset said PME registers;

wherein said PME registers receiving said reset signal and generating a power management signal, wherein if said power management signal is enabled said power management registers being capable of advanced power management states, and if said power management signal is disabled said power management registers not being capable of advanced power management states;

further comprising blocking circuitry receiving said power management signal and a conventional reset signal and generating a second reset signal for resetting said PCI and Cardbus registers;

wherein said blocking circuitry configured so that if said power management signal is disabled and said conventional reset signal is enabled, said second reset signal is enabled; and

further configured so that if said power management signal is enabled and said conventional reset signal is enabled or disabled, said second reset signal is disabled.

16. A controller as claimed in claim 15, said blocking circuitry comprising an AND gate receiving said conventional reset signal and said power management signal and said second reset signal.

17. A controller as claimed in claim 16, said AND gate configured so that said second reset signal is active if said power management signal is disabled and said conventional reset signal is active.

18. A controller as claimed in claim 16, said AND gate configured so that said second reset signal is not active if said power management signal is enabled.

19. A controller as claimed in claim 15, wherein said conventional reset signal comprising a PCI reset signal.

20. A controller as claimed in claim 15, wherein said trigger signal is the AUXVCC signal defined by the advanced power management specification (ACPI).

21. A controller as claimed in claim 15, wherein said power on reset circuitry adapted to generate said reset signal before said trigger signal reaches a predetermined threshold power level.

22. A controller as claimed in claim 21, wherein said trigger signal comprises an AUTXVCC signal, and said circuitry comprising an RC circuit chosen to generate said first reset signal.

23. A controller as claim 15, wherein said power on reset circuitry comprising a flip-flop circuit, said trigger signal is a conventional reset signal, and wherein said flip-flop adapted to receive said trigger signal and a signal that changes state only when said power is first applied to said registers and generate said first signal.

24. A controller as claimed in claim 23, wherein said trigger signal comprising a PCI reset signal, said PCI reset signal changing states when said power is first applied to said register and thereafter changing states based on external reset commands and wherein once said PCI reset signal changes state twice, said flip-flop circuit being adapted to permanently disable said first reset signal until said signal changes state again when said power is first applied to said system.

25. A controller as claimed in claim 15, wherein said power on reset circuitry adapted to generate said first reset signal and reset said PME registers only when power is first applied to said registers.