Combined waveform and data entry apparatus and method for facilitating fast behavorial verification of digital hardware designs

• US 6,675,310 B1
• Filed: 05/04/2000
• Issued: 01/06/2004
• Est. Priority Date: 05/04/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Escoto, Rodrigo Jose, Bloom, Andrew Maurice
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US09/564,730
• Time in Patent Office: 1,342 Days
• Field of Search: 713/400, 713/500, 713/501, 713/503, 713/600, 716/1, 716/3, 716/4, 716/6, 716/18
• US Class Current: 713/500
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A computer implemented apparatus and method that automates the entry, modification, analysis, and generation of test benches from electrical circuits, both of which are specified as hardware description language (HDL) files. The computer implemented-method and apparatus also provides a unique mechanism that blends entry and display of timing requirements that must be met by the electric circuit.

Claims

1. A computer system for constructing HDL test benches based upon HDL descriptions of electrical circuits, comprising:

means for generating and modifying said HDL data descriptions;

a computer including a monitor and memory storage means, said memory storage means containing instructions for displaying, on said monitor, a spreadsheet comprised of timing waveforms superimposed on an array of cells containing time-varying signal data patterns, wherein said waveforms and said data patterns correspond to said HDL descriptions and are simultaneously displayed on said monitor;

means for modifying said waveforms and said signal data patterns; and

means for automatically translating said waveforms into a complete HDL test bench file, said test bench file being fully compatible with industry-standard HDL simulators.

2. The computer system of claim 1 wherein said spreadsheet comprises rows and columns, said rows representing signal names and said columns representing cell values of said time varying signal data patterns, wherein said waveforms are superimposed upon said cell values.

3. The computer system of claim 1 wherein said signal data patterns are represented in binary form.

4. The computer system of claim 1 wherein said signal data patterns are represented in hexadecimal form.

5. The computer system of claim 1 wherein said signal data patterns are represented in decimal form.

6. The computer system of claim 1 wherein said waveforms are automatically revised to correspond to updates in said HDL descriptions.

7. The computer system of claim 1 wherein said means for modifying said waveforms and said signal data patterns is via one or more click events initiated by the user.

8. The computer system of claim 2 wherein if a user does not manually enter a cell value in a column, said cell value in said column is identical to the cell value in the column immediately proceeding said column but is not displayed therein.

9. The computer system of claim 1 further comprising means for updating said waveforms subsequent to simulation of said test bench by said HDL simulator.

10. A computer-aided method for constructing HDL test benches based upon HDL descriptions of electrical circuits, comprising the steps of:

generating and modifying said HDL description;

providing a computer including a monitor and memory storage means;

displaying on said monitor, a spreadsheet comprised of timing waveforms superimposed on an array of cells containing time-varying signal data patterns, wherein said waveforms and said data patterns correspond to said HDL descriptions and are simultaneously displayed on said monitor;

modifying signal waveforms and said data patterns; and

translating, automatically, said waveforms into a complete HDL test bench file, said test bench file being fully compatible with industry-standard HDL simulators.

11. The computer-aided method of claim 10 wherein said spreadsheet comprises rows and columns, said rows representing signal names and said columns representing cell values of said time varying signal data patterns, wherein said waveforms are superimposed upon said cell values.

12. The computer-aided method of claim 10 wherein said signal data patterns are represented in binary form.

13. The computer-aided method of claim 10 wherein said signal data patterns are represented in hexadecimal form.

14. The computer-aided method of claim 10 wherein said signal data patterns are represented in decimal form.

15. The computer-aided method of claim 10 wherein said waveforms are automatically modified to correspond to updates in said HDL descriptions.

16. The computer-aided method of claim 10 wherein said modifying said signal waveforms and said signal data patterns is via one or more click events initiated by the user.

17. The computer-aided method of claim 11 wherein if a user does not manually enter a cell value in a column, said cell value in said column is identical to the cell value in the column immediately proceeding said column but is not displayed therein.

18. The computer-aided method of claim 10 further comprising means for updating said waveforms subsequent to simulation of said test bench by said HDL simulator.

19. A computer program stored in a computer-readable medium, said computer program causing said computer to perform a method of constructing HDL test benches based upon HDL descriptions of electrical circuits, said method comprising the steps of:

generating and modifying said HDL description;

providing a computer including a monitor;

displaying on said monitor, a spreadsheet comprised of timing waveforms superimposed on an array of cells containing time-varying signal data patterns, wherein said waveforms and said data patterns correspond to said HDL descriptions and are simultaneously displayed on said monitor;

modifying signal waveforms and said data patterns; and

translating, automatically, said waveforms into a complete HDL test bench file, said test bench file being fully compatible with industry-standard HDL simulators.

20. The computer program of claim 19 wherein said spreadsheet comprises rows and columns, said rows representing signal names and said columns representing cell values of said time varying signal data patterns, wherein said waveforms are superimposed upon said cell values.

21. The computer program of claim 19 wherein said signal data patterns are represented in binary form.

22. The computer program of claim 19 wherein said signal data patterns are represented in hexadecimal form.

23. The computer program of claim 19 wherein said signal data patterns are represented in decimal form.

24. The computer program of claim 19 wherein said waveforms are automatically revised to correspond to updates in said HDL descriptions.

25. The computer program of claim 19 wherein said modifying said signal waveforms and said signal data patterns is via one or more click events initiated by the user.

26. The computer program of claim 19 wherein if a user does not manually enter a cell value in a column, said cell value in said column is identical to the cell value in the column immediately proceeding said column but is not displayed therein.

27. The computer program of claim 19 further comprising means for updating said waveforms subsequent to simulation of said test bench by said HDL simulator.