Method and device for synchronizing and testing a processor and a monitoring circuit

• US 6,675,320 B1
• Filed: 07/17/2000
• Issued: 01/06/2004
• Est. Priority Date: 10/01/1998
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Schumacher, Hartmut, Ringger, Klaus
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): MCCARTHY, CHRISTOPHER S
• Application Number:
  US09/555,156
• Time in Patent Office: 1,268 Days
• Field of Search: 714/12, 714/47, 714/51, 714/23, 714/44, 701/36, 701/45, 701/39, 701/42, 701/48, 701/70, 701/76, 701/92, 701/97, 701/33, 701/29, 713/500, 713/400
• US Class Current: 714/12
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/1675 Temporal synchronisation or re-synchronisation of redundant processing components
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits

Abstract

The invention relates to a method and apparatus for synchronizing at least one computer, having at least one monitoring circuit associated with this computer. The synchronization takes place through at least one transmitted signal (WDS) in the form of a double pulse from the computer (μC) to the peripheral components (PIC1, PIC2), which contain the monitoring circuits. To that end, shortly after the computer (μC) is started up at system start or after an HW reset, the signal (WDS) is sent to the at least one peripheral component (PIC1, PIC2). After this, the upper and lower limit of the signal sequence (WDS) to be regularly transmitted by the computer for the monitoring circuit are tested and therefore the function of the monitoring circuits is tested. As with the synchronization, the testing takes place with a reaction of the monitoring circuits by means of at least one acknowledgement signal (IRS1, IRS2, R).

Claims

1. A method for operating at least one computer and at least one monitoring circuit associated with the at least one computer for safety devices in vehicles, wherein the at least one computer and the at least one monitoring circuit exchange at least one signal, whereby the at least one computer and the at least one monitoring circuit are synchronized by means of the at least one signal, characterized In that the at least one signal is embodied as a pulse sequence of at least two separate pulses, wherein the spacing of the two pulses is chosen to be smaller than the duration of a pulse reset signal from the at least one monitoring circuit.

2. The method according to claim 1, characterized in that after the at least one computer and the at least one monitoring circuit have been synchronized, the monitoring circuit is tested as to its function, wherein by means of the transmission or non-transmission of at least one test signal by the at least one computer, a reaction caused by this in the form of at least one reset signal, of the at least one monitoring circuit, is tested.

3. The method according to claim 2, characterized in that the at least one signal by means of which the at least one computer and the at least one monitoring circuit are synchronized and/or the at least one test signal are embodied as a pulse sequence of at least two separate pulses.

4. An apparatus with at least one computer and at least one monitoring circuit associated with the at least one computer for safety devices in vehicles, wherein the at least one computer and the at least one monitoring circuit exchange at least one signal, whereby the at least one computer and the at least one monitoring circuit are synchronized by means of the at least one signal characterized in that the at least signal is embodied as a pulse sequence of at least two separate pulses, wherein the spacing of the two pulses is chosen to be smaller than the duration of a pulse reset signal from the at least one monitoring circuit.

5. An apparatus with at least one computer and at least one monitoring circuit associated with the at least one computer for safety devices in vehicles, wherein the at least one computer and the at least one monitoring circuit exchange at least one signal, whereby the at least one computer and the at least one monitoring circuit are synchronized by means of the at least one signal characterized in that the at least one computer is associated with at least two independent monitoring circuits, and the at least one signal is embodied as a pulse sequence of at least two separate pulses, wherein the spacing of the two pulses is chosen to be smaller than the duration of a pulse reset signal from the at least one monitoring circuit.

6. The apparatus according to claim 5, characterized in that the at least one computer and the at least two monitoring circuits associated with it are synchronized by means of the at least one signal.