Method and system for predicting worst-case capacitive and inductive switching vector
First Claim
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1. A method for determining a worst case switching vector in a circuit network, wherein the circuit network is represented as including a victim node and a plurality of attacker nodes, comprising:
- (a) setting the victim node to function as an attacker node and the attacker nodes to function as victim nodes;
(b) applying a test signal to the victim node;
(c) determining a response signal Ni[t] for each attacker node generated by the application of the test signal to the victim node;
(d) determining a time instant associated with a maximum noise; and
, (e) determining a phase for each response signal at the time instant of maximum noise.
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Abstract
A method and system for determination of the worst case switching vector, which greatly reduces the search space complexity. A single simulation is performed in the time-domain wherein the roles of the victim and attacker conductors are switched. In particular, the search space is reduced by virtue of the fact that certain combinations for the behavior attacker conductors are excluded. Only the phases of the attacker signals need to be determined.
187 Citations
18 Claims
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1. A method for determining a worst case switching vector in a circuit network, wherein the circuit network is represented as including a victim node and a plurality of attacker nodes, comprising:
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(a) setting the victim node to function as an attacker node and the attacker nodes to function as victim nodes;
(b) applying a test signal to the victim node;
(c) determining a response signal Ni[t] for each attacker node generated by the application of the test signal to the victim node;
(d) determining a time instant associated with a maximum noise; and
,(e) determining a phase for each response signal at the time instant of maximum noise. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
if Ni[m]≧
0 setting V[i] to a first value;
if Ni[m]<
0 setting V[i] to a second value.
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5. The method according to claim 3, further comprising:
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(a) if the victim node is held low, using the worst case switching vector V[i] in a noise simulation by applying a rising input to each node for which V[i] equals a first value and applying a falling input to each node for which V[i] equals a second value;
(b) if the victim node is held high, using the worst case switching vector in a noise simulation by applying a falling input to each node for which V[i] equals the first value and applying a rising input to each node for which V[i] equals the second value.
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6. The method according to claim 1, wherein the conductors in the network are substantially identical in composition.
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7. The method according to claim 1, wherein the conductors in the network comprise a linear network.
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8. The method according to claim 1, further comprising determining a total response signal S[t] by summing each of the response signals Ni[t] associated with the victim nodes N for each time sample t, according to the relationship:
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wherein W is the window length and T is the time period of total response signal.
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9. The method according to claim 8, further comprising generating a worst case switching vector V for each response signal Ni[t] by:
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10. A system for determining a worst case switching vector in a circuit network, wherein the circuit network is represented as including a victim node and a plurality of attacker nodes, comprising:
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a central processing unit (“
CPU”
), wherein the CPU is adapted to;
set the victim node to function as an attacker node and the attacker nodes to function as victim nodes;
apply a test signal to the victim node;
determine a response signal Ni[t] for each attacker node generated by the application of the test signal to the victim node;
determine a time instant associated with a maximum noise; and
,determine a phase for each response signal at the time instant of maximum noise. - View Dependent Claims (11, 12, 13, 14, 15, 16)
if Ni[m]≧
0 setting V[i] to a first value;
if Ni[m]<
0 setting V[i] to a second value.
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14. The system according to claim 10, wherein the conductors in the network comprise a linear network.
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15. The system according to claim 10, wherein the conductors in the network comprise a linear network.
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16. The system according to claim 10, wherein the CPU:
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(a) if the victim node is held low, utilizes the worst case switching vector V[i] in a noise simulation by applying a rising input to each node for which V[i] equals a first value and applying a falling input to each node for which V[i] equals a second value, (b) if the victim node is held high, utilizes the worst case switching vector V[i] in a noise simulation by applying a falling input to each node for which V[i] equals the first value and applying a rising input to each node for which V[i] equals the second value.
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17. A program storage device storing instructions executable by a CPU including instructions for determining a worst case switching vector in a circuit network, wherein the circuit network is represented as including a victim node and a plurality of attacker nodes, comprising instructions for:
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setting the victim node to function as an attacker node and the attacker nodes to function as victim nodes;
applying a test signal to the victim node;
determining a response signal Ni[t] for each attacker node generated by the application of the test signal to the victim node;
determining a time instant associated with a maximum noise; and
,determining a phase for each response signal at the time instant of maximum noise. - View Dependent Claims (18)
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Specification
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Current AssigneeIntel Corporation
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Original AssigneeIntel Corporation
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InventorsElzinga, Mark
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Primary Examiner(s)Smith, Matthew
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Assistant Examiner(s)Kik, Phallaka
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Application NumberUS10/024,403Publication NumberTime in Patent Office753 DaysField of Search716/6, 716/2, 703/16US Class Current716/113CPC Class CodesG06F 30/367 Design verification, e.g. u...
